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The ADCCON2.SDIV bits select the decimation rate, thereby also the resolution and time required to
complete a conversion, and hence the sample rate. The decimation rate should only be changed when no
conversion is running.
The last channel of a sequence is selected with the ADCCON2.SCH bits as described previously.
The ADCCON3 register controls the channel number, reference voltage, and decimation rate for a single
conversion. The single conversion takes place immediately after the ADCCON3 register is written to, or if a
conversion sequence is ongoing, immediately after the sequence has ended. The coding of the register
bits is exactly as for ADCCON2.
12.2.5 ADC Conversion Results
The digital conversion result is represented in 2s-complement form. For single-ended configurations, the
result can be expected to be positive. This is because the result is the difference between the input signal
and ground, which is always positively signed (Vconv = Vinp – Vinn, where Vinn = 0 V). The maximum
value is reached when the input signal is equal to VREF, the selected voltage reference. For differential
configurations, the difference between two pins is converted, and this difference can be negatively signed.
For example, with a decimation rate of 512 using only the 12 MSBs of the digital conversion result
register, the maximum value of 2047 is reached when the analog input (Vconv) is equal to VREF, and
minimum value of –2048 is reached when the analog input is equal to –VREF.
The digital conversion result is available in ADCH and ADCL when ADCCON1.EOC is set to 1. Note that the
conversion result always resides in the MSB section of the combined ADCH and ADCL registers.
When the ADCCON2.SCH bits are read, they indicate the channel on which conversion is ongoing. The
results in ADCL and ADCH normally apply to the previous conversion. If the conversion sequence has
ended, ADCCON2.SCH has a value of one more than the last channel number, but if the channel number
last written to ADCCON2.SCH was 12 or more, the same value is read back.
12.2.6 ADC Reference Voltage
The positive reference voltage for analog-to-digital conversions is selectable as either an internally
generated voltage, the AVDD5 pin, an external voltage applied to the AIN7 input pin, or a differential
voltage applied to the AIN6–AIN7 inputs.
The accuracy of the conversion results depend on the stability and noise properties of the reference
voltage. Offset from the wanted voltage introduces a gain error in the ADC proportional to the ratio of the
wanted voltage and the actual voltage. Noise on the reference must be lower than quantization noise of
the ADC to ensure the specified SNR is achieved.
12.2.7 ADC Conversion Timing
The ADC should only be used with the 32-MHz XOSC, and no system clock division should be
implemented by the user. The actual ADC sampling frequency of 4 MHz is generated by fixed internal
division. The time required to perform a conversion depends on the selected decimation rate. In general,
the conversion time is given by:
Tconv = (decimation rate + 16) × 0.25 μs.
12.2.8 ADC Interrupts
The ADC generates an interrupt when a single conversion triggered by writing to ADCCON3 has completed.
No interrupt is generated when a conversion from the sequence is completed.
12.2.9 ADC DMA Triggers
The ADC generates a DMA trigger every time a conversion from the sequence has completed. When a
single conversion completes, no DMA trigger is generated.
There is one DMA trigger for each of the eight channels defined by the first eight possible settings for
ADCCON2.SCH. The DMA trigger is active when a new sample is ready from the conversion for the
channel. The DMA triggers are named ADC_CHsd in
differential channel.
SWRU191F – April 2009 – Revised April 2014
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8-1, where s is single-ended channel and d is
ADC Operation
135
ADC
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