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16.1 Watchdog Mode
The WDT is disabled after a system reset. To start the WDT in watchdog mode, the WDCTL.MODE[1:0]
bits must be set to 10. The Watchdog Timer counter then starts incrementing from 0. When the timer is
enabled in watchdog mode, it is not possible to disable the timer. Therefore, writing 00 or 01 to
WDCTL.MODE[1:0] has no effect if the WDT is already operating in Watchdog mode.
The WDT operates with a Watchdog Timer clock frequency of 32.768 kHz (when the 32-kHz XOSC is
used). This clock frequency gives time-out periods equal to 1.9 ms, 15.625 ms, 0.25 s, and 1 s,
corresponding to the count value settings 64, 512, 8192, and 32,768, respectively.
If the counter reaches the selected timer interval value, the Watchdog Timer generates a reset signal for
the system. If a watchdog clear sequence is performed before the counter reaches the selected timer
interval value, the counter is reset to 0 and continues incrementing its value. The watchdog clear
sequence consists of writing 0xA to WDCTL.CLR[3:0], followed by writing 0x5 to the same register bits
within one watchdog clock period. If this complete sequence is not performed before the end of the
watchdog period, the Watchdog Timer generates a reset signal for the system.
When the WDT has been enabled in watchdog mode, it is not possible to change the mode by writing to
the WDCTL.MODE[1:0] bits, and the timer interval value cannot be changed.
In watchdog mode, the WDT does not produce interrupt requests.
16.2 Timer Mode
To start the WDT in timer mode, the WDCTL.MODE[1:0] bits must be set to 11. The timer is started and
the counter starts incrementing from 0. When the counter reaches the selected interval value, the timer
produces an interrupt request (IRCON2.WDTIF or IEN2.WDTIE). When the counter reaches the selected
interval value, the timer produces an interrupt request, using IRCON2.WDTIF as the interrupt flag and
IEN2.WDTIE as the interrupt mask.
In timer mode, it is possible to clear the timer contents by writing a 1 to WDCTL.CLR[0]. When the timer
is cleared, the content of the counter is set to 0. Writing 00 to WDCTL.MODE[1:0] stops the timer and
clears it to 0.
The timer interval is set by the WDCTL.INT[1:0] bits. The interval cannot be changed during timer
operation, and should be set when the timer is started. In timer mode, a reset is not produced when the
timer interval has been reached.
Note that if the watchdog mode is selected, the timer mode cannot be selected before the chip is reset.
16.3 Watchdog Timer Register
This section describes the register, WDCTL, for the Watchdog Timer.
SWRU191F – April 2009 – Revised April 2014
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Watchdog Mode
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Watchdog Timer
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