Register Settings Update; Register Access Modes; Example Hardware Structure For The R* Register Access Mode; Registers That Require Update From Their Default Value - Texas Instruments CC253x User Manual

Registers

23.15.1 Register Settings Update

This section contains a summary of the register settings that must be updated from their default value to
have optimal performance.
The following settings should be set for both RX and TX. Although not all settings are necessary for both
RX and TX, it is recommended for simplicity (allowing one set of settings to be written at the initialization
of the code).
Table 23-6. Registers That Require Update From Their Default Value
Register Name
AGCCTRL1
TXFILTCFG
FSCAL1

23.15.2 Register Access Modes

The Mode column in
column gives the meaning of the different alternatives.
Mode
R Read
W Write
R0 Read constant zero
R1 Read constant one
W1 Only possible to write one
W0 Only possible to write zero
R* The value read is not the actual register value, but rather the value seen by the module. This is typically used where a
configuration value may be generated automatically (through calibration, dynamic control, and so forth) or manually
overridden with a register value. An example structure is shown for the AGCCTRL2 register in
read_data
write_ data
Figure 23-24. Example Hardware Structure for the R* Register Access Mode
256
CC253x Radio
New Value (Hex)
0x15 Adjusts AGC target value
0x09 Sets TX anti-aliasing filter to appropriate bandwidth
0x00 Recommended setting for lowest spurious emission
Table 23-7 shows what kind of accesses are allowed for each bit. The Description
Table 23-7. Register-Bit Access Modes
LNA_ CURRENT_OE
AGCCTRL2
Register
AGC
Module
Copyright © 2009–2014, Texas Instruments Incorporated
Description
Description
rf_ input
1
0
SWRU191F – April 2009 – Revised April 2014
www.ti.com
Figure 23-24.
LNA
B0308-01
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