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1.1.1 CPU and Memory
The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access buses
(SFR, DATA, and CODE/XDATA) with single-cycle access to SFR, DATA, and the main SRAM. It also
includes a debug interface and an 18-input extended interrupt unit. The detailed functionality of the CPU
and the memory is addressed in
The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of
which is associated with one of four interrupt priorities. Any interrupt service request is serviced also when
the device is in idle mode by going back to active mode. Some interrupts can also wake up the device
from sleep mode (when in sleep mode, the device is in one of the three low-power modes PM1, PM2, or
PM3); see
Chapter 4
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the
physical memories and all peripherals through the SFR bus. The memory arbiter has four memory access
points, access of which can map to one of three physical memories: SRAM, flash memory, and
XREG/SFR registers. The memory arbiter is responsible for performing arbitration and sequencing
between simultaneous memory accesses to the same physical memory.
The 4-, 6-, or 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces.
The SRAM is an ultralow-power SRAM that retains its contents in all power modes. This is an important
feature for low-power applications.
The 32-, 64-, 96-, 128-, or 256-KB flash block provides in-circuit programmable non-volatile program
memory for the device, and maps into the CODE and XDATA memory spaces. In addition to holding
program code and constants, the non-volatile memory allows the application to save data that must be
preserved such that it is available after restarting the device. Using this feature one can, for example, use
saved network-specific data to avoid the need for a full start-up and network find-and-join process.
1.1.2 Clocks and Power Management
The digital core and peripherals are powered by a 1.8-V low-dropout voltage regulator
Additionally, the CC253x, CC2540, and CC2541 contain a power-management functionality that allows the
use of different low-power modes (PM1, PM2, and PM3) for low-power applications with a long battery life
(see
Chapter 4
for more details). Five different reset sources exist to reset the device; see
more details.
1.1.3 Peripherals
The CC253x, CC2540, and CC2541 include many different peripherals that allow the application designer
to develop advanced applications. Not all peripherals are present on all devices. See
of which peripherals are present on each device.
The debug interface
circuit debugging. Through this debug interface, it is possible to perform an erasure of the entire flash
memory, control which oscillators are enabled, stop and start execution of the user program, execute
supplied instructions on the 8051 core, set code breakpoints, and single-step through instructions in the
code. Using these techniques, it is possible to perform in-circuit debugging and external flash
programming elegantly.
The device contains flash memory for storage of program code. The flash memory is programmable from
the user software and through the debug interface (as mentioned previously). The flash controller
(Chapter
6) handles writing and erasing the embedded flash memory. The flash controller allows page-
wise erasure and 4-bytewise programming.
The I/O controller
whether peripheral modules control certain pins or whether they are under software control, and if so,
whether each pin is configured as an input or output and if a pullup or pulldown resistor in the pad is
connected. CPU interrupts can be enabled on each pin individually. Each peripheral that connects to the
I/O pins can choose between two different I/O pin locations to ensure flexibility in various applications.
SWRU191F – April 2009 – Revised April 2014
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Chapter
2.
for more details.
(Chapter
3) implements a proprietary two-wire serial interface that is used for in-
(Chapter
7) is responsible for all general-purpose I/O pins. The CPU can configure
Copyright © 2009–2014, Texas Instruments Incorporated
Overview
(Chapter
26).
Chapter 5
for
Table 0-1
for a listing
21
Introduction
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