Texas Instruments CC253x User Manual
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Texas Instruments CC253x User Manual

System-on-chip for 2.4ghz
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CC253x System-on-Chip Solution for 2.4-GHz
IEEE 802.15.4 and ZigBee
Applications
®
A
CC2540/41 System-on-Chip Solution for 2.4-
GHz Bluetooth
low energy Applications
®
User's Guide
Literature Number: SWRU191F
April 2009 – Revised April 2014

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  • Page 1 CC253x System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee Applications ® CC2540/41 System-on-Chip Solution for 2.4- GHz Bluetooth low energy Applications ® User's Guide Literature Number: SWRU191F April 2009 – Revised April 2014...

  • Page 2: Table Of Contents

    Debug Interface and Power Modes ........................Registers ................... Power Management and Clocks ..................Power Management Introduction .................... 4.1.1 Active and Idle Modes ......................... 4.1.2 ......................... 4.1.3 Contents SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 3 DMA Configuration Parameters ....................8.2.1 Source Address ....................8.2.2 Destination Address ..................... 8.2.3 Transfer Count ....................... 8.2.4 VLEN Setting ....................... 8.2.5 Trigger Event SWRU191F – April 2009 – Revised April 2014 Contents Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 4 ......................11.2 Timer Compare ......................11.3 Timer Capture ....................11.4 Sleep Timer Registers ................................................12.1 ADC Introduction ......................12.2 ADC Operation Contents SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 5 Baud-Rate Generation ......................17.5 USART Flushing ......................17.6 USART Interrupts ....................17.7 USART DMA Triggers ......................17.8 USART Registers ......................Operational Amplifier SWRU191F – April 2009 – Revised April 2014 Contents Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 6 22.1.2 Up Counter ....................22.1.3 Timer Overflow ..................22.1.4 Timer Delta Increment ....................22.1.5 Timer Compare ....................22.1.6 Overflow Count ..................22.1.7 Overflow-Count Update Contents SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 7 23.9.7 Frame-Check Sequence ................23.9.8 Acknowledgement Transmission ......................23.10 RXFIFO Access .................. 23.10.1 Using the FIFO and FIFOP ....................23.10.2 Error Conditions SWRU191F – April 2009 – Revised April 2014 Contents Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 8 25.11 Packet Sniffing ........................25.12 Registers ..................... 25.12.1 Register Overview ..................25.12.2 Register Settings Update ................... 25.12.3 SFR Register Descriptions ......................Voltage Regulator Contents SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 9 27.5 Z-Stack™ Software (www.ti.com/z-stack) ...................... 27.6 BLE Stack Software ........................Abbreviations ....................... Additional Information ................. Texas Instruments Low-Power RF Web Site ..................Low-Power RF Online Community .............. Texas Instruments Low-Power RF Developer Network ..................... Low-Power RF eNewsletter ........................References ........................
  • Page 10 ............23-3. Schematic View of the IEEE 802.15.4 Frame Format [1] ................23-4. Format of the Frame Control Field (FCF) List of Figures SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 11 25-12. Timing of Packets in RX Tasks ..................25-13. Timing of Packets in TX Tasks ..................... 25-14. Complete Appended Packet SWRU191F – April 2009 – Revised April 2014 List of Figures Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 12 25-2. Commands to FIFO via RFST Register ....................25-3. Access to FIFO Registers ....................25-4. RAM-Based Registers ..................25-5. Address Structure for Auto Mode List of Tables SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 13 25-24. Registers That Should Be Updated From Their Default Value, Bit Rates 1 Mbps and Lower ........ 25-25. Registers That Should Be Updated From Their Default Value, Bit Rate 2 Mbps SWRU191F – April 2009 – Revised April 2014 List of Tables Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 14: Preface

    CC2540F128/CC2540F256 and CC2541F128/CC2541F256 constitute the market’s most comprehensive single-mode Bluetooth low energy solution. The CC253x System-on-Chip solution for 2.4 GHz is suitable for a wide range of applications. These can easily be built on top of the IEEE 802.15.4 based standard protocols (RemoTI™ network protocol, TIMAC software, and Z-Stack™...

  • Page 15: Cc253X Family Overview

    Also visit the Low Power RF, ZigBee, and Bluetooth low energy sections of the TI E2E Community (www.ti.com/lprf-forum), where you can easily get in touch with other CC253x, CC2540, and CC2541 users and find FAQs, Design Notes, Application Notes, Videos, and so forth.

  • Page 16: Register Bit Conventions

    Read and write Read-only Read as 0 Read as 1 Write-only Write as 0 Write as 1 Hardware clear Hardware set Read This First SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 17: Introduction

    In order to help the user to develop these applications, this user's guide focuses on the usage of the different building blocks of the CC253x, CC2540, and CC2541 device family. For detailed device descriptions, complete feature lists, and performance numbers, see the device-specific...

  • Page 18: Overview

    Figure 1-3 show the different building blocks of the CC253x and, CC2540, and CC2541 devices. Not all features and functions of all modules or peripherals are present on all devices of the CC253x, CC2540, and CC2541; hence, see the device-specific data sheet for a device-specific block diagram.

  • Page 19: Cc2540 Block Diagram

    The modules can be roughly divided into one of three categories: CPU and memory related modules; modules related to peripherals, clocks, and power management; and radio-related modules. SWRU191F – April 2009 – Revised April 2014 Introduction Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 20: Cc2541 Block Diagram

    TIMER 1 (16-Bit) TIMER 2 (BLE LL TIMER) TIMER 3 (8-bit) RF_P RF_N TIMER 4 (8-bit) DIGITAL ANALOG MIXED Figure 1-3. CC2541 Block Diagram Introduction SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 21: Cpu And Memory

    Five different reset sources exist to reset the device; see Chapter 5 more details. 1.1.3 Peripherals The CC253x, CC2540, and CC2541 include many different peripherals that allow the application designer to develop advanced applications. Not all peripherals are present on all devices. See Table 0-1 for a listing of which peripherals are present on each device.
  • Page 22 FIFO memory combined with DMA access ensures that a minimum of CPU involvement is needed for USB communication. Introduction SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 23: Radio

    (Section B.2) and by subscribing to the Low-Power RF eNewsletter (Section B.4). To contact a third-party to help with development or to use modules, check out the Texas Instruments Low-Power RF Developer Network (Section B.3). SWRU191F – April 2009 – Revised April 2014...

  • Page 24: 8051 Cpu

    ........................... Topic Page ..................8051 CPU Introduction ......................Memory ....................CPU Registers ..................Instruction Set Summary ......................Interrupts 8051 CPU SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 25: 8051 Cpu Introduction

    8051 mapping where only the program memory (that is, flash memory) is mapped to CODE memory space. This mapping is the default after a device reset and is shown in Figure 2-2. SWRU191F – April 2009 – Revised April 2014 8051 CPU Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 26: Xdata Memory Space (Showing Sfr And Data Mapping)

    8051 DATA SPACE SRAM SIZE – 256 SRAM (SRAM_SIZE Bytes) 0x0000 M0097-02 Figure 2-1. XDATA Memory Space (Showing SFR and DATA Mapping) 8051 CPU SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 27: Cpu Memory Space

    DATA memory space. The 8-bit address range of DATA memory is mapped into the upper 256 bytes of the SRAM, that is, the address range from (SRAM_SIZE – 256) through (SRAM_SIZE – 1). SWRU191F – April 2009 – Revised April 2014 8051 CPU Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 28: Physical Memory

    IEEE 802.15.4 or Bluetooth low energy compliant devices a unique IEEE address from the TI range of addresses. For CC253x, this is a 64-bit IEEE address stored with least-significant byte first at XDATA address 0x780C. For CC2540 and CC2541, this is a 48-bit IEEE address stored with least-significant byte first at XDATA address 0x780E.

  • Page 29: Sfr Overview

    — Reserved — 0xB0 — Reserved — 0xB7 — Reserved — 0xC8 — Reserved P0IFG 0x89 Port 0 interrupt status flag SWRU191F – April 2009 – Revised April 2014 8051 CPU Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 30 Timer 1 channel 1 capture or compare control T1CCTL2 0xE7 Timer 1 Timer 1 channel 2 capture or compare control T1STAT 0xAF Timer 1 Timer 1 status 8051 CPU SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 31 U1UCR 0xFB USART 1 USART 1 UART control U1GCR 0xFC USART 1 USART 1 generic control WDCTL 0xC9 Watchdog Timer control SWRU191F – April 2009 – Revised April 2014 8051 CPU Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 32: Overview Of Xreg Registers

    Table 2-2 gives a descriptive overview of the register address space. Table 2-2. Overview of XREG Registers XDATA Address Register Name Description Radio registers (see CC253x Radio Section 23.15 or CC2540 0x6000–0x61FF — Radio Section 24.1 or CC2541 Radio Section 25.12...

  • Page 33: Xdata Memory Access

    The flash-bank map register, FMAP, controls mapping of physical 32-KB code banks to the program address region 0x8000–0xFFFF in CODE memory space. SWRU191F – April 2009 – Revised April 2014 8051 CPU Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 34: Cpu Registers

    0x00 Data pointer-0, high byte DPL0 (0x82) – Data Pointer-0 Low Byte Name Reset Description DPL0[7:0] 0x00 Data pointer-0, low byte 8051 CPU SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 35: Registers

    Parity flag, parity of accumulator set by hardware to 1 if it contains an odd number of 1s; otherwise it is cleared to 0. SWRU191F – April 2009 – Revised April 2014 8051 CPU Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 36: Accumulator

    127 bytes relative to first byte of the following instruction. • bit – Direct addressed bit in DATA area or SFR 8051 CPU SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 37: Instruction Set Summary

    Exclusive OR indirect RAM to accumulator 66–67 XRL A,#data Exclusive OR immediate data to accumulator XRL direct,A Exclusive OR accumulator to direct byte SWRU191F – April 2009 – Revised April 2014 8051 CPU Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 38 SJMP rel Short jump (relative address) JMP @A+DPTR Jump indirect relative to the DPTR JZ rel Jump if accumulator is zero 8051 CPU SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 39 OR complement of direct bit to carry MOV C,bit Move direct bit to carry flag MOV bit,C Move carry flag to direct bit SWRU191F – April 2009 – Revised April 2014 8051 CPU Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 40: Interrupts

    The interrupts are grouped into a set of priority-level groups with selectable priority levels. The interrupt-enable registers are described in Section 2.5.1 and the interrupt priority settings are described in Section 2.5.3. 8051 CPU SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 41: Interrupt Masking

    (1) (2) Timer 2 0x53 IEN1.T2IE IRCON.T2IF Hardware-cleared when interrupt service routine is called Additional IRQ mask and IRQ flag bits exist. SWRU191F – April 2009 – Revised April 2014 8051 CPU Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 42 Port 1 inputs P1INT 0x7B IEN2.P1IE IRCON2.P1IF RF general interrupts 0x83 IEN2.RFIE S1CON.RFIF Watchdog overflow in timer mode 0x8B IEN2.WDTIE IRCON2.WDTIF 8051 CPU SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 43: Interrupt Overview

    Interrupts www.ti.com Interrupt Priority Bits Figure 2-4. Interrupt Overview SWRU191F – April 2009 – Revised April 2014 8051 CPU Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 44 Timer 1 interrupt enable 0: Interrupt disabled 1: Interrupt enabled DMAIE DMA transfer interrupt enable 0: Interrupt disabled 1: Interrupt enabled 8051 CPU SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 45: Interrupt Processing

    EA, the CPU may enter the interrupt routine on the cycle following this instruction. If that happens, the interrupt routine is executed with EA set to 0, which may delay the service of higher-priority interrupts. SWRU191F – April 2009 – Revised April 2014 8051 CPU Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 46 Both flags are set when the radio requests the interrupt. 0: Interrupt not pending 1: Interrupt pending 8051 CPU SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 47: Interrupt Priority

    While an interrupt service request is in progress, it cannot be interrupted by a lower- or same-level interrupt. SWRU191F – April 2009 – Revised April 2014 8051 CPU Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 48: Priority Level Setting

    Table 2-7. Interrupt Priority Groups Group Interrupts IPG0 RFERR IPG1 P2INT IPG2 URX0 UTX0 IPG3 URX1 UTX1 IPG4 P1INT IPG5 P0INT 8051 CPU SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 49: Interrupt Polling Sequence

    Table 2-8. Interrupt Polling Sequence Interrupt Number Interrupt Name RFERR URX0 URX1 Polling sequence ↓ P0INT P2INT UTX0 UTX1 P1INT SWRU191F – April 2009 – Revised April 2014 8051 CPU Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 50: Debug Interface

    Page ...................... Debug Mode ..................Debug Communication ....................Debug Commands .................... Flash Programming ............... Debug Interface and Power Modes ......................Registers Debug Interface SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 51: Debug Mode

    Bit 6 Bit 5 Bit 4 Bit 3 Bit 0 Bit 2 Bit 1 T0303-01 Figure 3-2. Transmission of One Byte SWRU191F – April 2009 – Revised April 2014 Debug Interface Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 52: Typical Command Sequence-No Extra Wait For Response

    Figure 3-4 shows how the wait works. Debug Interface SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 53: Debug Commands

    RD_CONFIG 0010 0XXX Read debug configuration data. Input byte: none. Output byte: Returns value set by WR_CONFIG command. See Table 3-2. SWRU191F – April 2009 – Revised April 2014 Debug Interface Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 54 The value 0 means 2048 data bytes; thus, the smallest number of bytes to transfer is 1. Input bytes: Command sequence Output byte: Debug status byte. See Table 3-3. Debug Interface SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 55: Debug Configuration

    CHIP_ERASE command is received and returns to low when the flash is fully erased. 0: – 1: Chip erase in progress SWRU191F – April 2009 – Revised April 2014 Debug Interface Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 56: Hardware Breakpoints

    Bits 2–0: Memory bank bits. Bits 18–16 of hardware breakpoint. The second data byte consists of bits 15–8 of the hardware breakpoint. Debug Interface SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 57: Flash Programming

    When the chip is in debug mode, the two options are controlled by configuration bit 5 (SOFT_POWER_MODE). SWRU191F – April 2009 – Revised April 2014 Debug Interface Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 58 NOTE: Debugging in Idle mode and PM1 is not supported. It is recommended to use active mode or another power mode when debugging. Debug Interface SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 59: Registers

    SRAM size in KB minus 1. For example, a 4-KB device has this field set to 011. Add dependent 1 to the number to get the number of KB available. SWRU191F – April 2009 – Revised April 2014 Debug Interface Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 60: Power Management And Clocks

    Power Management Introduction ................Power-Management Control ................Power-Management Registers ..................Oscillators and Clocks ..................Timer Tick Generation ....................Data Retention Power Management and Clocks SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 61: Power Management Introduction

    3VBOD) that senses on the unregulated voltage. The purpose of this 3VBOD is to reduce the current consumption of the device when supplied with voltages well below the operating voltage. SWRU191F – April 2009 – Revised April 2014 Power Management and Clocks Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 62: Active And Idle Modes

    (setting PCON.IDLE). If CLKCONCMD.OSC was 1 when PCON.IDLE was set, when entering the power mode, it continues to run at 16 MHz. Power Management and Clocks SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 63: Power-Management Registers

    This bit is always read as 0. All enabled interrupts clear this bit when active, and the device re-enters active mode. SWRU191F – April 2009 – Revised April 2014 Power Management and Clocks Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 64 10: Watchdog Timer reset 11: Clock loss reset – Reserved CLK32K The 32-kHz clock signal (synchronized to the system clock) Power Management and Clocks SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 65: Clock System Overview

    Sleep Timer SLEEPCMD.MODE[1:0] Watchdog Timer XTAL2 32-kHz Crystal Oscillator SLEEPCMD.MODE[1:0] 32-kHz RC Oscillator SLEEPCMD.OSC32K_CALDIS B0303-02 Figure 4-1. Clock System Overview SWRU191F – April 2009 – Revised April 2014 Power Management and Clocks Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 66: Oscillators And Clocks

    The 16 MHz RC oscillator is calibrated once after the 32-MHz XOSC has been selected and is stable, that is, when the CLKCONSTA.OSC bit switches from 1 to 0. Power Management and Clocks SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 67: 32-Khz Oscillators

    This section describes the oscillator and clock registers. All register bits retain their previous values when entering PM2 or PM3. SWRU191F – April 2009 – Revised April 2014 Power Management and Clocks Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 68 CLKCONCMD.CLKSPD should be set to 000 when CLKCONCMD.OSC = 0 or to 001 when CLKCONCMD.OSC = 1. Power Management and Clocks SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 69: Timer Tick Generation

    Switching to the PM2 or PM3 low-power modes appears transparent to software. Note that the value of the Sleep Timer is not preserved in PM3. All registers retain their values in PM1. SWRU191F – April 2009 – Revised April 2014 Power Management and Clocks Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 70: Reset

    ........................... Topic Page ............... Power-On Reset and Brownout Detector ................... Clock-Loss Detector Reset SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 71: Power-On Reset And Brownout Detector

    32-MHz XOSC. CLD (0x6290) – Clock-Loss Detection Name Reset Description – 0000 000 Reserved Clock-loss detector enable 0: Detector disabled 1: Detector enabled SWRU191F – April 2009 – Revised April 2014 Reset Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 72: Flash Controller

    Topic Page ................. Flash Memory Organization ......................Flash Write ....................Flash Page Erase ..................... Flash DMA Trigger ................... Flash Controller Registers Flash Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 73: Flash Memory Organization

    = 111, the clock period is only 4 μs. It is therefore recommended to keep CLKCONSTA.CLKSPD at 000 or 001 while writing to the flash. SWRU191F – April 2009 – Revised April 2014 Flash Controller Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 74: Writing Multiple Times To A Word

    DMA channel is configured and how a DMA transfer is initiated to write a block of data from a location in XDATA to flash memory. Flash Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 75: Cpu Flash Write

    Timer is enabled, a Watchdog Timer interval must be selected that is longer than 20 ms, the duration of the flash page-erase operation, so that the CPU can clear the Watchdog Timer. SWRU191F – April 2009 – Revised April 2014 Flash Controller Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 76: Performing Flash Erase From Flash Memory

    DMA has high priority so the transfer is not interrupted. If interrupted for more than 20 μs, the write operation times out and FCTL.WRITE bit is cleared. Flash Controller Registers The flash controller registers are described in this section. Flash Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 77 FADDRL (0x6271) – Flash-Address Low Byte Name Reset Description FADDRL[7:0] 0x00 Low byte of flash word address SWRU191F – April 2009 – Revised April 2014 Flash Controller Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 78: I/O Ports

    Debug Interface ..................... 32-kHz XOSC Input ................... Radio Test Output Signals ................. 7.10 Power-Down Signal MUX (PMUX) ...................... 7.11 I/O Registers I/O Ports SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 79: Unused I/O Pins

    SFR registers P0IEN, P1IEN, and P2IEN. Even I/O pins configured as peripheral I/O or general-purpose outputs have interupts generated when enabled. SWRU191F – April 2009 – Revised April 2014 I/O Ports Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 80: General-Purpose I/O Dma

    RX pin prior to taking it in use as a UART pin. I/O Ports SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 81: Timer 1

    7-1, the Timer 3 signals are shown as the following: • 0: Channel 0 capture or compare pin • 1: Channel 1 capture or compare pin SWRU191F – April 2009 – Revised April 2014 I/O Ports Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 82: Timer 4

    TX: TXDATA • RT: RTS • CT: CTS SPI: • MI: MISO • MO: MOSI • C: SCK • SS: SSN I/O Ports SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 83: Adc

    32-kHz XOSC when CLKCONCMD.OSC32K is low, regardless of register settings. The port pins are set in analog mode when CLKCONCMD.OSC32K is low. SWRU191F – April 2009 – Revised April 2014 I/O Ports Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 84: Radio Test Output Signals

    • OBSSEL0: Observation output control register 0 • OBSSEL1: Observation output control register 1 • OBSSEL2: Observation output control register 2 I/O Ports SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 85 P0SEL (0xF3) – Port 0 Function Select Name Reset Description 0x00 P0.7 to P0.0 function select SELP0_[7:0] General-purpose I/O Peripheral function SWRU191F – April 2009 – Revised April 2014 I/O Ports Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 86 P0.7 to P0.0 I/O direction Input Output P1DIR (0xFE) – Port 1 Direction Name Reset Description DIRP1_[7:0] 0x00 P1.7 to P1.0 I/O direction Input Output I/O Ports SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 87 0000 00 R/W P1.7 to P1.2 I/O input mode Pullup or pulldown [see P2INP (0xF7) – Port 2 input mode] 3-state – Reserved SWRU191F – April 2009 – Revised April 2014 I/O Ports Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 88 Port 2, inputs 4 to 0 interrupt status flags. When an input port pin has an interrupt request pending, the corresponding flag bit is set. I/O Ports SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 89 USB D+ interrupt disabled USB D+ interrupt enabled P2_[4:0]IEN 0 0000 R/W Port P2.4 to P2.0 interrupt enable Interrupts are disabled. Interrupts are enabled. SWRU191F – April 2009 – Revised April 2014 I/O Ports Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 90 Select output signal on observation output 2 111 1011 (123): rfc_obs_sig0 111 1100 (124): rfc_obs_sig1 111 1101 (125): rfc_obs_sig2 Others: Reserved I/O Ports SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 91 Select output signal on observation output 5 111 1011 (123): rfc_obs_sig0 111 1100 (124): rfc_obs_sig1 111 1101 (125): rfc_obs_sig2 Others: Reserved SWRU191F – April 2009 – Revised April 2014 I/O Ports Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 92: Dma Controller

    DMA Configuration Setup ..................Stopping DMA Transfers ....................DMA Interrupts ............... DMA Configuration-Data Structure ..................DMA Memory Access ....................DMA Registers DMA Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 93: Dma Operation

    A DMAREQ bit is cleared only when the corresponding DMA transfer occurs. The DMAREQ bit is not cleared when the channel is disarmed. SWRU191F – April 2009 – Revised April 2014 DMA Controller Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 94: Dma Operation

    DMAARMn = 0 If IRQMASK == 1 then Count? Mode? = 1) IRCON.DMAIF Block Transfer Mode? F0033-01 Figure 8-1. DMA Operation DMA Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 95: Dma Configuration Parameters

    The transfer count can be defined in the configuration or it can be defined as variable-length, as described in Section 8.2.4. SWRU191F – April 2009 – Revised April 2014 DMA Controller Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 96: Vlen Setting

    Decrement by one. The address pointer decrements one count after each transfer. where a count equals 1 byte in byte mode and 2 bytes in word mode. DMA Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 97: Dma Transfer Mode

    DMA0CFGH:DMA0CFGL gives the start address for the DMA channel 0 configuration data structure. DMA1CFGH:DMA1CFGL gives the start address for the DMA channel 1 configuration data structure, followed by the channel 2–4 configuration-data structures. SWRU191F – April 2009 – Revised April 2014 DMA Controller Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 98: Stopping Dma Transfers

    Timer 4, compare, channel 1 Sleep Timer (not in Sleep Timer compare CC2540/41) RADIO1 Radio (CC2541) Radio DMA trigger 1 (see Section 25.3.2) DMA Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 99: Dma Configuration-Data Structure

    USART 1 USART 1 TX complete FLASH Flash controller Flash data write complete RADIO Radio (not in CC2540) CC253x: RF packet byte received (see Section 23.3) CC2541: Radio DMA trigger 0 (see Section 25.3.2) ADC_CHALL ADC end of a conversion in a sequence, sample ready...
  • Page 100 PRIORITY[1:0] The DMA channel priority: Low, CPU has priority. Assured, DMA at least every second try High, DMA has priority Reserved DMA Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 101: Dma Registers

    DMA0CFGL (0xD4) – DMA Channel-0 Configuration Address Low Byte Name Reset Description DMA0CFG[7:0] 0x00 The DMA channel 0 configuration address, low-order SWRU191F – April 2009 – Revised April 2014 DMA Controller Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 102 DMA channel transfer complete or interrupt pending DMAIF0 R/W0 DMA channel-0 interrupt flag DMA channel transfer not complete DMA channel transfer complete or interrupt pending DMA Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 103: Timer 1 (16-Bit Timer)

    ..................9.11 Timer 1 DMA Triggers ..................... 9.12 Timer 1 Registers ..............9.13 Accessing Timer 1 Registers as Array SWRU191F – April 2009 – Revised April 2014 Timer 1 (16-Bit Timer) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 104: 16-Bit Counter

    The free-running mode can be used to generate independent time intervals and output-signal frequencies. FFFFh 0000h OVFL OVFL T0308-01 Figure 9-1. Free-Running Mode Timer 1 (16-Bit Timer) SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 105: Modulo Mode

    The channel mode is set for each channel with its control and status register, T1CCTLn. The settings include input capture and output compare modes. SWRU191F – April 2009 – Revised April 2014 Timer 1 (16-Bit Timer) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 106: Input Capture Mode

    H-bridge. The delay or dead-time can be obtained in the PWM outputs by using T1CCn as shown in the following: Timer 1 (16-Bit Timer) SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 107: Initial Compare Output Values (Compare Mode)

    (100) T1CCn Clear when equal T1CC0, set when equal (101) Set when equal T1CC0, clear when equal T1CCn (110) SWRU191F – April 2009 – Revised April 2014 Timer 1 (16-Bit Timer) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 108: Output Compare Modes, Timer Free-Running Mode

    6 - Set When T1CC0, Clear When T1CCn T1CCn T1CC0 T1CCn T1CC0 T0311-01 Figure 9-4. Output Compare Modes, Timer Free-Running Mode Timer 1 (16-Bit Timer) SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 109: Output Compare Modes, Timer Modulo Mode

    6 - Set When T1CC0, Clear When T1CCn T1CCn T1CC0 T1CCn T1CC0 T0312-01 Figure 9-5. Output Compare Modes, Timer Modulo Mode SWRU191F – April 2009 – Revised April 2014 Timer 1 (16-Bit Timer) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 110: Output Compare Modes, Timer Up-And-Down Mode

    6 - Set When T1CC0, Clear When T1CCn T1CCn T1CCn T1CCn T1CCn T1CC0 T1CC0 T0313-01 Figure 9-6. Output Compare Modes, Timer Up-and-Down Mode Timer 1 (16-Bit Timer) SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 111: Ir Signal Generation And Learning

    The output of Timer 1 channel 1 is ANDed with that of Timer 3 channel 1 to form the IR output as shown Figure 9-7 SWRU191F – April 2009 – Revised April 2014 Timer 1 (16-Bit Timer) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 112: Non-Modulated Codes

    0x0000. The compare values must be updated once every period by the DMA or CPU if they are not to be kept the same. Timer 1 (16-Bit Timer) SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 113: Learning

    T1_CH2, which are generated on timer compare events as follows: • T1_CH0 – Channel 0 compare • T1_CH1 – Channel 1 compare • T1_CH2 – Channel 2 compare SWRU191F – April 2009 – Revised April 2014 Timer 1 (16-Bit Timer) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 114: Timer 1 Registers

    Modulo, repeatedly count from 0x0000 to T1CC0. Up-and-down, repeatedly count from 0x0000 to T1CC0 and from T1CC0 down to 0x0000. Timer 1 (16-Bit Timer) SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 115 T1CC0[7:0] until, and at the same time as, a later write to T1CC0H takes effect. SWRU191F – April 2009 – Revised April 2014 Timer 1 (16-Bit Timer) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 116 T1CC1[7:0] until, and at the same time as, a later write to T1CC1H takes effect. Timer 1 (16-Bit Timer) SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 117 T1CC2[7:0] until, and at the same time as, a later write to T1CC2H takes effect. SWRU191F – April 2009 – Revised April 2014 Timer 1 (16-Bit Timer) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 118 T1CC3[7:0] until, and at the same time as, a later write to T1CC3H takes effect. Timer 1 (16-Bit Timer) SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 119: Accessing Timer 1 Registers As Array

    0x62A0–0x62A4. The 16-bit capture or compare values are mapped to 0x62A6–0x62AF; 0x62A5 is unused. SWRU191F – April 2009 – Revised April 2014 Timer 1 (16-Bit Timer) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 120: Timer 3 And Timer 4 (8-Bit Timers)

    10.7 Timer 3 and Timer 4 DMA Triggers ................10.8 Timer 3 and Timer 4 Registers Timer 3 and Timer 4 (8-Bit Timers) SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 121: 8-Bit Timer Counter

    0 or 1. The settings include capture and compare modes. SWRU191F – April 2009 – Revised April 2014 Timer 3 and Timer 4 (8-Bit Timers) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 122: Input Capture Mode

    • Counter reaches terminal count value. • Compare event Timer 3 and Timer 4 (8-Bit Timers) SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 123: Timer 3 And Timer 4 Dma Triggers

    Modulo, repeatedly count from 0x00 to T3CC0 Up-and-down, repeatedly count from 0x00 to T3CC0 and down to 0x00 SWRU191F – April 2009 – Revised April 2014 Timer 3 and Timer 4 (8-Bit Timers) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 124 (compare mode) causes the T3CC0.VAL[7:0] update to the written value to be delayed until T3CNT.CNT[7:0] = 0x00. Timer 3 and Timer 4 (8-Bit Timers) SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 125 Name Reset Description CNT[7:0] 0x00 Timer count byte. Contains the current value of the 8-bit counter SWRU191F – April 2009 – Revised April 2014 Timer 3 and Timer 4 (8-Bit Timers) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 126 (compare mode) causes the T4CC0.VAL[7:0] update to the written value to be delayed until T4CNT.CNT[7:0] = 0x00. Timer 3 and Timer 4 (8-Bit Timers) SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 127 Interrupt is pending. T3OVFIF R/W0 Timer 3 overflow interrupt flag No interrupt is pending. Interrupt is pending. SWRU191F – April 2009 – Revised April 2014 Timer 3 and Timer 4 (8-Bit Timers) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 128: Sleep Timer

    24-bit capture ........................... Topic Page ......................11.1 General ....................11.2 Timer Compare ....................11.3 Timer Capture ..................11.4 Sleep Timer Registers Sleep Timer SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 129: General

    This sequence, using the rising edge on P0.0 as an example, is shown in Figure 11-1. Failure to follow the procedure may cause the capture functionality to stop working until a chip reset. SWRU191F – April 2009 – Revised April 2014 Sleep Timer Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 130: Sleep Timer Registers

    Sleep Timer count. When writing, this register sets the high bits [23:16] of the compare value. The value read is latched at the time of reading register ST0. The value written is latched when ST0 is written. Sleep Timer SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 131 STCV2 (0x62B4) – Sleep Timer Capture Value Byte 2 Name Reset Description STCV[23: 0x00 Bits [23:16] of Sleep Timer capture value SWRU191F – April 2009 – Revised April 2014 Sleep Timer Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 132: Adc

    Conversion results can be written to memory through DMA. Several modes of operation are available..........................Topic Page ....................12.1 ADC Introduction ....................12.2 ADC Operation SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 133: Adc Introduction

    Note that the reference in this case must not be dependent on the battery voltage; for instance, the AVDD5 voltage must not be used as a reference. SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 134: Adc Conversion Sequences

    The ADCCON2 register controls how the sequence of conversions is performed. ADCCON2.SREF is used to select the reference voltage. The reference voltage should only be changed when no conversion is running. SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 135: Adc Conversion Results

    ADCCON2.SCH. The DMA trigger is active when a new sample is ready from the conversion for the channel. The DMA triggers are named ADC_CHsd in Table 8-1, where s is single-ended channel and d is differential channel. SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 136: Adc Registers

    – Controls the 16-bit random-number generator. See ADCCON1 (0xB4) – ADC Control 1 description in Section 14.3. – Reserved. Always set to 11 SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 137 AIN5 0110: AIN6 0111: AIN7 1000: AIN0–AIN1 1001: AIN2–AIN3 1010: AIN4–AIN5 1011: AIN6–AIN7 1100: 1101: Reserved 1110: Temperature sensor 1111: VDD / 3 SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 138 Set to 1 to connect the temperature sensor to the SOC_ADC. See also ATEST register description ADCTM to enable the temperature sensor in Section 23.15.3 (CC253x) or Section 24.1 (CC2540) or Section 25.12.3 (CC2541). SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 139: Battery Monitor

    Functionality and Usage of the Battery Monitor ......... 13.2 Using the Battery Monitor for Temperature Monitoring ................. 13.3 Battery Monitor Registers SWRU191F – April 2009 – Revised April 2014 Battery Monitor Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 140: Functionality And Usage Of The Battery Monitor

    Table 13-1. Values Showing How Different Temperatures Relate to BATTMON_VOLTAGE for a Typical Device BATTMON_VOLTAGE Temperature –40°C –26°C –11°C 7°C 25°C 47°C 70°C 97°C 128°C Battery Monitor SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 141: Battery Monitor Registers

    BATTMON_VOLTAGE, an output of BATTMON_OUT = 1 tells that the temperature is above 70°C, whereas BATTMON_OUT = 0 tells that it is below 70°C. 13.3 Battery Monitor Registers This section describes the battery monitor registers. SWRU191F – April 2009 – Revised April 2014 Battery Monitor Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 142 0: Supply voltage (AVDD5) 1: Voltage from the temperature sensor, which must be enabled using the ATEST.ATEST_CTRL register; described in Section 23.15.3 Battery Monitor SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 143: Random-Number Generator

    This chapter provides information about the random-number generator and its usage..........................Topic Page ..................... 14.1 Introduction ..............14.2 Random-Number-Generator Operation ..............14.3 Random-Number-Generator Registers SWRU191F – April 2009 – Revised April 2014 Random-Number Generator Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 144: Introduction

    RNDL. For the CC253x, when a random value is required, the LFSR should be seeded by writing RNDL with random bits from the IF_ADC in the RF receive path. To use this seeding method, the radio must first be powered on.

  • Page 145: Random-Number-Generator Registers

    Normal operation. (13× unrolling) Clock the LFSR once (13× unrolling) Reserved Stopped. Random-number generator is turned off. – Reserved. Always set to 11 SWRU191F – April 2009 – Revised April 2014 Random-Number Generator Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 146: Aes Coprocessor

    Modes of Operation ......................15.6 CBC-MAC ....................... 15.7 CCM Mode ....................15.8 AES Interrupts .................... 15.9 AES DMA Triggers ....................15.10 AES Registers AES Coprocessor SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 147: Aes Operation

    Before the last block is loaded, the mode is changed to CBC. The last block is downloaded and the block uploaded is the message MAC. SWRU191F – April 2009 – Revised April 2014 AES Coprocessor Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 148: Ccm Mode

    When encrypting message blocks using CTR mode, the CTR value must be any value but zero. The content of the encryption-flag byte is described in Figure 15-4. AES Coprocessor SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 149: Message Encryption Phase Block

    11. The encrypted authentication data U is appended to the encrypted message. This gives the final result, C. Result C = encrypted message(m) + U SWRU191F – April 2009 – Revised April 2014 AES Coprocessor Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 150: Aes Interrupts

    The AES coprocessor registers have the layout shown in this section. The registers return to their reset value when the chip enters PM2 or PM3. AES Coprocessor SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 151 Reset Description DIN[7:0] 0x00 Encryption input data ENCDO (0xB2) – Encryption Output Data Name Reset Description DOUT[7:0] 0x00 Encryption output data SWRU191F – April 2009 – Revised April 2014 AES Coprocessor Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 152: Watchdog Timer

    ........................... Topic Page ....................16.1 Watchdog Mode ...................... 16.2 Timer Mode .................. 16.3 Watchdog Timer Register Watchdog Timer SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 153: Watchdog Mode

    Note that if the watchdog mode is selected, the timer mode cannot be selected before the chip is reset. 16.3 Watchdog Timer Register This section describes the register, WDCTL, for the Watchdog Timer. SWRU191F – April 2009 – Revised April 2014 Watchdog Timer Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 154 Clock period × 512 (approximately 15.625 ms) Clock period × 64 (approximately 1.9 ms) For CC253x and CC2540, when clock division is enabled through CLKCONCMD.CLKSPD, the length of the watchdog timer interval is reduced by a factor equal to the current oscillator clock frequency divided by the set clock speed.

  • Page 155: Usart

    SSN Slave-Select Pin ..................17.4 Baud-Rate Generation ....................17.5 USART Flushing ..................... 17.6 USART Interrupts ..................17.7 USART DMA Triggers ....................17.8 USART Registers SWRU191F – April 2009 – Revised April 2014 USART Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 156: Uart Mode

    Transmission of a byte does not occur before the CTS input goes low. USART SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 157: Uart Character Format

    If the external slave requires a slave-select signal, this can be implemented through software using a general-purpose I/O pin. SWRU191F – April 2009 – Revised April 2014 USART Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 158: Spi Slave Operation

    Table 17-1. Commonly Used Baud-Rate Settings for 32 MHz System Clock Baud Rate (bps) UxBAUD.BAUD_M UxGCR.BAUD_E Error (%) 2400 0.14 4800 0.14 9600 0.14 14,400 0.03 19,200 0.14 USART SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 159: Usart Flushing

    (x refers to the USART number, that is, 0 or 1): • UxCSR, USART x control and status • UxUCR, USART x UART control SWRU191F – April 2009 – Revised April 2014 USART Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 160 USART transmit or receive active status. In SPI slave mode, this bit equals slave select. USART idle USART busy in transmit or receive mode USART SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 161 Description Baud-rate mantissa value. BAUD_E along with BAUD_M decides the UART baud rate and the BAUD_M[7:0] 0x00 SPI master SCK clock frequency. SWRU191F – April 2009 – Revised April 2014 USART Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 162 UART start-bit level. Ensure that the polarity of the start bit is opposite the level of the idle line. Low start bit High start bit USART SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 163 BAUD_M[7:0] 0x00 BAUD_E BAUD_M Baud rate mantissa value. along with determines the UART baud rate and the SPI master SCK clock frequency. SWRU191F – April 2009 – Revised April 2014 USART Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 164: Operational Amplifier

    Ideal for use in combination with the onboard ADC in sensor applications ........................... Topic Page ...................... 18.1 Description ....................... 18.2 Calibration ....................18.3 Clock Source ......................18.4 Registers Operational Amplifier SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 165: Description

    W1/R0 Operational amplifier enable OPAMPS (0x62C1) – Operational Amplifier Status Name Reset Description – 0000 000 Reserved CAL_BUSY Calibration in progress SWRU191F – April 2009 – Revised April 2014 Operational Amplifier Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 166: Analog Comparator

    The analog comparator (in the CC2530, CC2531, CC240 and CC2541) has the following features: • Low-power operation • Wake-up source ........................... Topic Page ...................... 19.1 Description ......................19.2 Register Analog Comparator SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 167: Description

    This section describes the registers for the analog comparator. CMPCTL (0x62D0) – Analog Comparator Control and Status Name Reset Description – 0000 00 Reserved Comparator enable Comparator output OUTPUT SWRU191F – April 2009 – Revised April 2014 Analog Comparator Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 168 C, the C bus must be connected to a normal GPIO in parallel..........................Topic Page ......................20.1 Operation ....................20.2 C Registers SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 169: Operation

    C data is communicated using the serial data (SDA) pin and the serial clock (SCL) pin. Both SDA and SCL are bidirectional and must be connected to a positive supply voltage using a pullup resistor. SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 170: C Initialization And Reset

    Data on SDA must be stable during the high period of SCL (see Figure 20-4). The state of SDA can only change when SCL is low, otherwise a START or STOP condition is generated. SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 171: C Addressing Modes

    C slave address is programmed with the I2CADDR.ADDR bits. The value of the I2CADDR.GC bit determines whether the slave responds to a general call. SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 172: Slave Transmitter Mode

    Switched to not-addressed SLV mode; own SLA or no action general-call address is recognized; START condition is transmitted when the bus becomes free. SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 173: Slave Receiver Mode

    Data byte is received and not-ACK is returned. address (0x00) Data byte is received and ACK is returned. has been no action received; ACK has been returned SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 174 Switched to not-addressed SLV mode; own SLA or no action general-call address is recognized; START condition is transmitted when the bus becomes free. SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 175: Master Transmitter Mode

    STOP condition is transmitted; STO flag is reset. no action STOP condition followed by a START condition is no action transmitted; STO flag is reset. SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 176: Master Receiver Mode

    STOP condition followed by a START condition is read data byte transmitted; STO flag is reset. SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 177: C Clock Generation And Synchronization

    State Period SCL From Device #1 SCL From Device #2 Bus Line Figure 20-8. Synchronization of Two I C Clock Generators During Arbitration SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 178: Bus Error

    C registers used for control and status of the I C module. The registers return to their reset values when the chip enters PM2 or PM3. SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 179: Clock Rates Defined At 32 Mhz

    C Own Slave Address Name Reset Description ADDR 0000 00 R/W Own slave address General-call address acknowledge. If set, the general-call address is recognized. SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 180 When I2CWC.SDAOE is set, reading SDAD reads the output register, not the pin. When I2CWC.SDAOE is cleared, reading SDAD reads the pin. Writing SDAD writes to the output register. SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 181: Usb Controller

    Endpoints 1–5 ........................ 21.8 ....................... 21.9 USB Reset ..................21.10 Suspend and Resume ..................... 21.11 Remote Wake-Up ....................21.12 USB Registers SWRU191F – April 2009 – Revised April 2014 USB Controller Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 182: Usb Introduction

    When the PLL has locked, it is safe to use the USB controller. Note: The PLL must be disabled before exiting active mode and re-enabled after entering active mode. USB Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 183: Usb Interrupts

    USBIIE.EP0IE. If the EP0 interrupt mask bit is set to 1, the CPU interrupt flag IRCON2.P2IF is also asserted. An interrupt request is only generated if IEN2.P2IE and USBIIE.EP0IE are both set to 1. SWRU191F – April 2009 – Revised April 2014 USB Controller Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 184: Error Conditions

    32 bytes denotes the end of the transfer. For isochronous transfers there would not be a handshake packet from the host. USB Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 185: Out Transactions (Rx State)

    OUT FIFO grows up from the bottom of the endpoint memory region. For isochronous transfers, there is no handshake packet from the device. SWRU191F – April 2009 – Revised April 2014 USB Controller Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 186: Double Buffering

    To enable double buffering for an IN endpoint, USBCSIH.IN_DBL_BUF must be set to 1. To enable double buffering for an OUT endpoint, set USBCSOH.OUT_DBL_BUF to 1. USB Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 187: Fifo Access

    USBOIE.OUTEPxIE. If the OUT EPx interrupt mask bit is set to 1, the CPU interrupt flag IRCON2.P2IF is also asserted. An interrupt request is only generated if IEN2.P2IE and USBOIE.OUTEPxIE are both set to 1. SWRU191F – April 2009 – Revised April 2014 USB Controller Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 188: Bulk Or Interrupt In Endpoint

    The AutoClear feature typically is not used for isochronous endpoints, because the packet size increases or decreases from frame to frame. USB Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 189: Dma

    USB descriptor, and that the USB host must grant the device the privilege to perform remote wakeup (through a SET_FEATURE request). SWRU191F – April 2009 – Revised April 2014 USB Controller Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 190: Usb Registers

    Interrupt flag for OUT endpoint 2. Cleared by hardware when read OUTEP1IF R, H0 Interrupt flag for OUT endpoint 1. Cleared by hardware when read – – Reserved USB Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 191 OUT endpoint 2 interrupt enable 0: Interrupt disbled 1: Interrupt enabled OUTEP1IE OUT endpoint 1 interrupt enable 0: Interrupt disbled 1: Interrupt enabled – Reserved SWRU191F – April 2009 – Revised April 2014 USB Controller Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 192 This register must not be set to a value greater than the available FIFO memory for the endpoint. USB Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 193 When the data packet has been sent, this bit is cleared, and an interrupt request (IN EP{1–5}) is generated if the interrupt is enabled. SWRU191F – April 2009 – Revised April 2014 USB Controller Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 194 FIFO. An interrupt request (OUT EP{1–5}) is generated if the interrupt is enabled. This bit should be cleared when the packet has been unloaded from the FIFO. USB Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 195 Endpoint 4 FIFO register. Reading this register unloads one byte from the EP4 OUT FIFO. Writing to this register loads one byte into the EP4 IN FIFO. SWRU191F – April 2009 – Revised April 2014 USB Controller Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 196 Endpoint 5 FIFO register. Reading this register unloads one byte from the EP5 OUT FIFO. Writing to this register loads one byte into the EP5 IN FIFO. USB Controller SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 197: Timer 2 (Mac Timer)

    Timer 2 is mainly used to provide timing for 802.15.4 command-strobe-processor algorithms and for general timekeeping in the 802.15.4 MAC layer on CC253x devices, for timekeeping in the BLE link layer on CC2540 and CC2541, and for general radio timekeeping when running the radio in proprietary mode on CC2541.

  • Page 198: Timer Operation

    Timer 2 (MAC Timer) SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 199: Overflow-Count Update

    • Timer compare 1 • Timer compare 2 • Overflow-count overflow • Overflow-count compare 1 • Overflow-count compare 2 SWRU191F – April 2009 – Revised April 2014 Timer 2 (MAC Timer) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 200: Event Outputs (Dma Trigger And Radio Events)

    Timer 2 has two event outputs, T2_EVENT1 and T2_EVENT2. These can be used as DMA triggers, as inputs to the radio, for conditions in conditional instructions in the CSP on CC253x, for use by the BLE stack on CC2540 and CC2541, or for timing TX or RX in CC2541 when running the radio in proprietary mode.

  • Page 201: Timer Synchronous Start

    ±1 in the calculated timer value compared to the ideal timer value, not taking clock inaccuracies into account. SWRU191F – April 2009 – Revised April 2014 Timer 2 (MAC Timer) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 202: Timer 2 Registers

    – Timer 2 interrupt masks • T2EVTCFG – Timer 2 event output configuration • T2CTRL – Timer 2 configuration Timer 2 (MAC Timer) SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 203: Internal Registers

    When reading the T2M0 register with T2MSEL.T2MSEL set to 000 and T2CTRL.LATCH_MODE set to 1, the timer (t2tim) and overflow counter (t2ovf) values are latched. SWRU191F – April 2009 – Revised April 2014 Timer 2 (MAC Timer) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 204 Indirectly returns/modifies bits [23:16] of an internal register, depending on the T2MSEL.T2MOVFSEL value. Reading this register with T2MSEL.T2MOVFSEL set to 000 returns the latched value of t2ovf[23:16]. T2IRQF (0xA1) – Timer 2 Interrupt Flags (CC253x and CC2540) Name Reset Function –...
  • Page 205 Set when the Timer 2 counter counts to the value set at t2_cmp1 TIMER2_PERF R/W0 Set when the Timer 2 counter would have counted to a value equal to t2_per, but instead wraps to 0. T2IRQM (0xA7) – Timer 2 Interrupt Mask (CC253x and CC2540) Name Reset Function –...
  • Page 206 Section 22.4 for more details regarding timer start and stop. Write 1 to start timer, write 0 to stop timer. When read, it returns the last written value. T2EVTCFG (0x9C) – Timer 2 Event Configuration (CC253x and CC2540) Name Reset Function –...
  • Page 207 0011: t2ovf_per_event 0100: t2ovf_cmp1_event 0101: t2ovf_cmp2_event 0110: Reserved 0111: No event 1000: t2ovf_long_cmp1_event 1001: t2ovf_long_cmp2_event 1010–1110: Reserved 1111: No event SWRU191F – April 2009 – Revised April 2014 Timer 2 (MAC Timer) Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 208: Cc253X Radio

    ................23.12 Random-Number Generation ........... 23.13 Packet Sniffing and Radio Test Output Signals ................23.14 Command Strobe Processor ......................23.15 Registers CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 209: Rf Core

    Each of the individual sources has its own enable and interrupt flags in the RF Core. Flags can be found in RFIRQF0, RFIRQF1, and RFIERRF. Interrupt masks can be found in RFIRQM0, RFIRQM1, and RFERRM. SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 210 SFD has been received or transmitted. 0: No interrupt pending 1: Interrupt pending ACT_UNUSED R/W0 Reserved 0: No interrupt pending 1: Interrupt pending CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 211 Frequency synthesizer failed to achieve lock after time-out, or lock is lost during reception. Receiver must be restarted to clear this error situation. 0: No interrupt pending 1: Interrupt pending SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 212 A complete frame has been transmitted. 0: Interrupt disabled 1: Interrupt enabled TXACKDONE An acknowledgment frame has been completely transmitted. 0: Interrupt disabled 1: Interrupt enabled CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 213: Fifo Access

    RF Core are located at addresses from 0x6180 to 0x61EF. Configuration registers, RXFIFO, and TXFIFO are all preserved during sleep modes. SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 214: Rxfifo

    PENDING_OR register bit and the SACK, SACKPEND, and SNACK strobes into account. 214 CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 215: Frequency And Channel Programming

    ) transmitted first for each symbol. The transmitted bit stream and the chip sequences are observable on GPIO pins P1[0:5]. See Chapter 7 for details on how to configure the GPIO to do this. SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 216: Modulation

    Q channels with one-half chip-period offset. This is illustrated for the zero-symbol in Figure 23-2. I-Phase Q-Phase M0107-01 = 0.5 μs Figure 23-2. I/Q Phases When Transmitting a Zero-Symbol Chip Sequence, t CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 217: Ieee 802.15.4-2006 Frame Format

    Intra PAN Reserved Destination Reserved Source enabled pending request addressing addressing mode mode Figure 23-4. Format of the Frame Control Field (FCF) SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 218: Transmit Mode

    TX command strobe is executed, as long as it does not generate TX underflow (see the error conditions listed in Section 23.8.5). CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 219: Retransmission

    (that is, the length byte) have been transmitted. 23.8.6 TX Flow Diagram Figure 23-6 summarizes the previous sections in a flow diagram: SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 220: Tx Flow

    TX strobe) TX strobe) TX strobe) F0035-01 Figure 23-6. TX Flow CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 221: Transmitted Frame Processing

    FCS in the TXFIFO, so software must generate the FCS and write it to the TXFIFO along with the rest of the MPDU. The hardware implementation of the FCS calculator is shown in Figure 23-9. See [1] for further details. SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 222: Interrupts

    RXENABLE registers. The command strobes provide a hard on-off mechanism, whereas RXENABLE manipulation provides a soft on-off mechanism. The receiver is turned on by the following actions: • The SRXON strobe: CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 223: Rx State Timing

    (5) Automatic acknowledgment transmission with correct timing, and correct setting of the frame-pending bit, based on the results from source address matching and FCS checking. Figure 23-10. Single Received Frame and Transmitted Acknowledgment Frame SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 224: Synchronization Header And Frame-Length Fields

    The value of the frame version subfield of the FCF cannot be higher than FRMFILT0.MAX_FRAME_VERSION. • The source and destination address modes cannot be reserved values (1). • Destination address: CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 225 RX_OVERFLOW or RX_FRM_ABORTED is generated before the filtering result is known. Figure 23-12 illustrates the three different scenarios (not including the overflow and abort-error conditions). SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 226: Filtering Scenarios (Exceptions Generated During Reception)

    Set FRMFILT1.ACCEPT_FT2_ACK after successfully starting a transmission with acknowledgment request, and clear the bit again after the acknowledgment frame has been received or the time-out has been reached. CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 227: Source Address Matching

    Software is responsible for allocating table entries and for making sure that active short and extended address entries do not overlap. There are separate enable bits for short and extended addresses: SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 228: Matching Algorithm For Short And Extended Addresses

    SRC_MATCH_DONE interrupt flag is set, regardless of the result. If a match is found, the SRC_MATCH_FOUND flag is also set immediately before SRC_MATCH_DONE. Figure 23-14 illustrates the timing of the setting of flags: CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 229: Interrupts Generated By Source Address Matching

    To increase the available time, clear the FSMCTRL.RX2RX_TIME_OFF bit. This adds another 192 μs, for a total of 368 μs. This also reduces the risk of RX overflow. SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 230: Frame-Check Sequence

    The data sequence number (DSN), which is taken automatically from the last received frame • The FCS, which is given implicitly CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 231: Acknowledgment Timing

    • Automatic control, using the AUTOPEND feature • Manual control, using the FRMCTRL1.PENDING_OR bit SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 232: Rxfifo Access

    – The last byte of a new frame is received, even if the FIFOP threshold is not exceeded. If so, FIFOP goes back to low at the next RXFIFO read access. CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 233: Error Conditions

    (128 μs) as specified by IEEE 802.15.4 [1]. The RSSI value is a 2s-complement signed number on a logarithmic scale with 1-dB steps. SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 234: Link Quality Indication

    RF Core, generation of automatic acknowledgment frames, and control of all analog RF calibration. CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 235: Main Fsm

    Radio-Control State Machine www.ti.com Figure 23-20. Main FSM SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 236: Random-Number Generation

    23-21. Note that the dc component is clearly visible. A histogram (32 bins) of the 20 million values is shown in Figure 23-22. CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 237: Packet Sniffing And Radio Test Output Signals

    (rfc_obs_sig); for example, for packet sniffing one needs the rfc_sniff_data for the packet sniffer data signal and rfc_sniff_clk for the corresponding clock signal. SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 238: Command Strobe Processor

    RFST. Failure to observe this rule can lead to incorrect program execution and corrupt instruction memory contents. However, Immediate Command Strobe instructions may be written to RFST (see Section 23.14.3). CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 239: Data Registers

    ISSTART command. To clear the program contents, use the ISCLEAR instruction. SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 240: Registers

    CSPCTRL (0x61E0) – CSP Control Bit Name Reset Description – 0000 000 Reserved. Read as 0 CSP MCU control input MCU_CTRL CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 241: Instruction Set Summary

    For undefined opcodes, the behavior of the CSP is defined as a no-operation strobe command (SNOP). SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 242: Instruction Set Summary

    SNOP: Do nothing. SSTOP: Stops the command strobe processor execution and invalidates any set label. An IRQ_CSP_STOP interrupt request is issued. 242 CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 243: Instruction Set Definition

    The Y register is decremented by 1. An original value of 0x00 underflows to 0xFF. Operation: Y = Y – 1 Opcode: 0xC4 23.14.9.3 DECX SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 244 The Y register is incremented by 1 if the result is less than M; otherwise, Y register is loaded with value M. Operation: Y = min(Y + 1, M) CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 245 X = X – 1 when MAC Timer overflow = true PC = PC while X > 0 PC = PC + 1 when X = 0 Opcode: 0xBC 23.14.9.11 SETCMP1 SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 246 PC = PC while MAC Timer compare = false PC = PC + 1 when MAC Timer compare = true Opcode: 0xB9 CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 247 If S = 0, re-execute the conditional jump (that is, busy loop until condition is false). Skipping past the last instruction in the command buffer results in an implicit STOP command. SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 248 RX. The instruction waits for the radio to acknowledge the command before executing the next instruction. Operation: SRXON CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 249 Disable RX or TX and frequency synthesizer. Description: The SRFOFF instruction disables RX or TX and the frequency synthesizer. Operation: SRFOFF Opcode: 0xDF SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 250 The SACKPEND instruction sends an acknowledge frame with the pending field set. The instruction waits for the radio to acknowledge the command before executing the next instruction. Operation: SACKPEND Opcode: 0xD7 CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 251 The ISSTOP instruction stops the CSP program execution and the IRQ_CSP_STOP interrupt flag is asserted. Operation: Stop execution Opcode: 0xE2 23.14.9.33 ISSTART SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 252 The ISTXON instruction immediately enables TX after calibration. The instruction waits for the radio to acknowledge the command before executing the next instruction. Operation: STXON_STRB CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 253 Flush RXFIFO buffer and reset demodulator Description: The ISFLUSHRX instruction immediately flushes the RXFIFO buffer and resets the demodulator. Operation: SFLUSHRX Opcode: 0xED SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 254 The ISNACK instruction immediately prevents sending of an acknowledge frame to the currently received frame. Operation: SNACK Opcode: 0xE8 23.14.9.46 ISCLEAR CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 255: Registers

    CSPPROG22 CSPPROG23 0x61D8 0x61DC 0x61E0 CSPCTRL CSPSTAT CSPX CSPY 0x61E4 CSPZ CSPT 0x61E8 RFC_OBS_CTRL0 0x61EC RFC_OBS_CTRL1 RFC_OBS_CTRL2 0x61F0 0x61F4 0x61F8 TXFILTCFG SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 256: Register Settings Update

    LNA_ CURRENT_OE rf_ input write_ data AGCCTRL2 Register Module B0308-01 Figure 23-24. Example Hardware Structure for the R* Register Access Mode CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 257: Register Descriptions

    00: Leave as it is 01: Invert MSB 10: Set MSB to 0 11: Set MSB to 1 – Reserved. Always write 0 SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 258 To ensure that an entry in the source matching table is not used while it is being updated, set the corresponding EXT_ADDR_EN bit to 0 while updating. CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 259 Reserved. Should not be used TXFIFO looping ignores underflow in TXFIFO and reads cyclically; infinite transmission. Send pseudorandom data from CRC, infinite transmission. SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 260 For example, if a 1 is written to one or more bit positions in this register, the corresponding bits are cleared in RXENMASK. CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 261 16 channels 5 MHz apart. The channels are numbered 11 through 26. For an IEEE 802.15.4-2006 compliant system, the only valid settings are thus FREQ[6:0] = 11 + 5 × (channel number – 11). SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 262 Calibration done or not started Calibration in progress – Gives the current state of the FIFO and frame-control (FFCTRL) finite-state FSM_FFCTRL_STATE[5:0] machine. CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 263 RX2RX_TIME_OFF Defines whether or not a 12-symbol time-out should be used after frame reception has ended. No time-out 12-symbol-period time-out SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 264 RXFIFOCNT (0x619B) – Number of Bytes in RXFIFO Name Reset Description RXFIFOCNT[7:0] 0x00 Number of bytes in the RXFIFO. Unsigned integer CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 265 TXLAST_PTR (0x61A2) – TXFIFO Pointer Name Reset Description 0x00 RAM address offset of the last byte +1 byte of the TXFIFO TXLAST_PTR[7:0] SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 266 (FREQEST_offset), which can be found in the data sheet of the device (Appendix C). Real FREQEST value = FREQEST – FREQEST_offset. CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 267 This threshold should be set higher than 0x0C. This feature is enabled by AGC_DR_XTND_EN. SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 268 11: 0-dB attenuation in AAF (reference level) Write 1 to override the AGC AAF control signals with the values stored in AAF_RP. AAF_RP_OE CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 269 Controls series resistance of AAF ADC_FF_ADJ[1:0] Adjust feedforward Control of DAC DWA scheme ADC_DAC_ROT 0: DWA (scrambling) disabled 1: DWA enabled SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 270 Set one of two RF modulation modes for RX/TX IEEE 802.15.4 compliant mode Reversed phase, non-IEEE compliant RESERVED Reserved. Do not write. CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 271 00 0010 : Enables the temperature sensor in the CC2533 (see also the TR0 register description in Section 12.2.10) Other values reserved. SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 272 Power amplifier power-down signal when PD_OVERRIDE = 1 PA_PD Voltage-controlled oscillator power-down signal when PD_OVERRIDE = 1 VCO_PD LO power-down signal when PD_OVERRIDE = 1 LODIV_PD CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 273 00 0000 R/W Controls which observable signal from RF Core is to be muxed out to rfc_obs_sigs[2]. See description of RFC_OBS_CTRL0 for details. SWRU191F – April 2009 – Revised April 2014 CC253x Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 274 Controls bias current to PA 00: IREF bias 01: IREF and IVREF bias 10: PTAT bias 11: Increased PTAT slope bias CC253x Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 275: Cc2540 And Cc2541 Bluetooth Low Energy Radio

    Chapter 25 for a description of the operation in that case..........................Topic Page ......................24.1 Registers SWRU191F – April 2009 – Revised April 2014 CC2540 and CC2541 Bluetooth low energy Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 276: Registers

    11 0001: High from when the access address has been transmitted until end of packet, low otherwise Other values reserved CC2540 and CC2541 Bluetooth low energy Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 277 00 0001: Enables the temperature sensor (see also the TR0 register description in Section 12.2.10). Other values reserved. SWRU191F – April 2009 – Revised April 2014 CC2540 and CC2541 Bluetooth low energy Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 278: Cc2541 Proprietary Mode Radio

    Packet Format ..................... 25.9 Link Layer Engine ................25.10 Random Number Generation ....................25.11 Packet Sniffing ......................25.12 Registers CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 279: Rf Core

    Due to the use of individual interrupt masks in the RF core, the interrupts coming from the RF core have two-layered masking, and care must be taken when processing these interrupts. The procedure is described as follows. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 280: Rf Core Data Memory

    Radio core hardware registers are located at XDATA addresses 0x6180–0x61F7. Figure 25-1 shows the mapping of radio memory to MCU XDATA memory space. CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 281: Fifos

    The use of the pointers is indicated in Figure 25-2. Last Packet n -Packets First Packet Free Space M0220-01 Figure 25-2. FIFO Pointers SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 282 The command register RFST can be used for sending commands to the FIFO. Commands in the range 0x80–0xFF are commands to the FIFO. Other commands are commands to the LLE; see Section 25.9.1. CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 283: Commands To Fifo Via Rfst Register

    LLE. The reset FIFO commands should only be run by the MCU between LLE tasks. They are marked with an asterisk in Table 25-3. Table 25-3. Access to FIFO Registers Register Read Access Write Access SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 284: Dma

    The radio DMA trigger source is selected in registers RFFDMA0 and RFFDMA1. See the register descriptions in Section 25.12 for details. CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 285: Ram-Based Registers

    Bit 7: SYNTH_ON 0: Turn off synthesizer when task is done. 1: Leave synthesizer running after task is done. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 286 0: Recalibrate the synthesizer before listening for new packets 1: Recalibrate the synthesizer only when the task starts 286 CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 287 For transmit on clear channel. Number of additional PRF_RSSI_COUNT 0x6006–0x6007 Sem1 RSSI measurements that must be below the RSSI limit before transmission takes place. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 288 Total number of packets transmitted PRF_LAST_RSSI 0x6079 Sem1/R RSSI of last received packet PRF_LAST_DCOFF 0x607A–0x607D Sem1/R DC offset of last received packet 288 CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 289: Address Structure For Auto Mode

    Note: Must not be set to 1 unless the peer uses fixed length RXLENGTH 0x01 Sem1 Maximum length of received packet (0–127) ADDRESS 0x02 Sem1 Address of packet SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 290: Address Structure For Basic Mode

    Sem1/R Number of packets received with CRC OK N_RXNOK 0x0B Sem1/R Number of packets received with CRC error 290 CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 291: Variables In Ram

    PN sequence given by the polynomial x + 1. The output is the same as the shift register feedback. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 292: Cc2500-Compatible Pn9 Whitening

    The CC2500-compatible whitener is enabled by bit W_PN9_EN of the BSP_MODE register. CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 293: Crc

    If whitening is enabled, calculated CRC bytes are whitened before transmission, and received CRC bytes are de-whitened before CRC checking. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 294: Crc Module

    + … + a BSP_P2 PRF_CRC_INIT[2] BSP_P3 PRF_CRC_INIT[3] BSP_P0 PRF_CRC_INIT[0] BSP_P1 PRF_CRC_INIT[1] + … + a BSP_P2 PRF_CRC_INIT[2] BSP_P3 PRF_CRC_INIT[3] 294 CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 295: Coprocessor Mode

    This should be repeated for each CRC byte. If whitening is enabled, the read back CRC bytes are whitened. The BSP must not be set in coprocessor mode while the LLE is processing a packet. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 296: Frequency And Channel Programming

    The sync word can be programmed to be from 16 to 32 bits. CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 297: Packet Format

    0–1 byte 0–255 bytes 0–4 bytes Handled by modem R0009-01 Figure 25-6. Air Interface Packet Format for Basic Mode SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 298: Air Interface Packet Format For Auto Mode

    0 to 127 bytes with a 10-bit header. The maximum packet length can be limited, see Section 25.9.2.3.1 Section 25.9.2.3.2 CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 299: Rx Fifo Packet Organization

    – IGN is 1 for packets that may be ignored by the MCU due to repeated sequence number and 0 otherwise. – CRC is 1 if there was a CRC error and 0 otherwise. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 300: Tx Fifo Packet Organization

    7 or X 0x6020 or 0x6120 7 or X 0x6040 or 0x6140 7 or X 0x6060 or 0x6160 0x6000 300 CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 301: Link Layer Engine

    01; that value should only be written by the TI BLE stack. In order to switch modes, the LLE must be reset; writing to LLECTRL.LLE_MODE_SEL while LLECTRL.LLE_EN is 1 has no effect. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 302: Command Register

    Note that a Timer 2 event 1 may be pending from before the LLE starts waiting; in that case, the task starts immediately. To clear a pending Timer 2 event 1, reset the LLE. To prevent CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 303 T2M0, T2M1, T2MOVF0, T2MOVF1, and T2MOVF2 when t2_cap and t2ovf_cap are selected using the T2MSEL register; see Chapter SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 304: Timer 2 Capture Settings

    Unpermitted parameter TASKERR_TXFIFO TX FIFO without available data when not permitted TASKERR_RXFIFO Overfull RX FIFO in TX task 304 CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 305 The tone lasts for a time given by the RAM register PRFX_TONE_DURATION. In order to get a smooth transition from tone to preamble, it is recommended to set PRFX_TONE_DURATION as given Table 25-15. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 306: Recommended Ram Register Settings For Start Tone

    (regardless of the setting in PRF_TASK_CONF.REPEAT). CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 307: Interrupt And Counter Operation For Received Messages

    If PRF_PKT_CONF.ADDR_LEN is 0, the first entry that is enabled for the received sync word is used. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 308: Interrupt And Counter Operation For Received Messages

    Table 25-17. Interrupt and Counter Operation for Received Messages CRC Result Ignore Length Counter Incremented Interrupt Raised PRF_ADDR_ENTRYn.N_RXOK > 0 RXOK PRF_ADDR_ENTRYn.N_RXOK RXEMPTY PRF_ADDR_ENTRYn.N_RXIGNORED RXIGNORED PRF_ADDR_ENTRYn.N_RXNOK RXNOK CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 309 00: Nothing happens • 01: Behaves as if a CMD_STOP was received • 10: Behaves as if a CMD_SHUTDOWN was received SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 310: End-Of-Receive Tasks

    It is up to the MCU to ensure that the calculated length field does not exceed 255. If PRF_TASK_CONF.MODE is 00, no length field is transmitted. CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 311 RX FIFO. If PRF_PKT_CONF.ADDR_LEN is 1, the address byte is compared against PRF_ADDR_ENTRYn.ADDRESS for the n that was used in transmission. If not matching, reception is stopped. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 312: Interrupt And Counter Operation For Received Ack Packets

    PRF_ADDR_ENTRYn.SEQSTAT.SEQ should then be incremented by one. These operations should only take place between tasks (that is, while the LLE does not have SEMAPHORE1). CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 313: End-Of-Transmit Tasks

    Received unknown command TASKERR_CMD had obtained sync, an RXTXABO interrupt is also raised. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 314 PRF_TASK_CONF.START_CONF is 1 while listening before any packet, the task ends immediately with TASK_NOCC as the end cause. Otherwise, nothing happens. CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 315: Additional Reasons For End-Of-Transmit On Clear-Channel Tasks

    PRF_SEARCH_TIME register. Setting this register to 0 disables the time-out. In case of a time-out, the task ends for a normal sync search, or a packet is retransmitted in case of an ACK sync search. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 316: Timing Of Packets In Rx Tasks

    If it is not possible to achieve the retransmission time, the packet is retransmitted as early as possible. CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 317: Rf Test Commands

    LLE to create any interrupts or to write any end cause. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 318: Random Number Generation

    // Set lowest possible frequency to avoid signals in ISM band FREQCTRL = 0x00; // Enable radio in RX without sync search while (RFST != 0); CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 319: Packet Sniffing

    R0015-01 Figure 25-14. Complete Appended Packet This allows for the external receiver to differentiate between RX and TX packets. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 320: Registers

    RFRXFWR RFRXFRD 0x61C8 RFRXFWP RFRXFRP RFRXFSWP RFRXFSRP 0x61CC RFTXFLEN RFTXFTHRS RFTXFWR RFTXFRD 0x61D0 RFTXFWP RFTXFRP RFTXFSWP RFTXFSRP 0x61D4 320 CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 321: Register Settings Update

    (assuming MSB first); set extra preamble bytes MDMCTRL3 6193 Set RSSI mode to peak detect after sync RXCTRL 619A Receiver currents SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 322: Sfr Register Descriptions

    1: Interrupt pending TXTHSHDN R/W0 TX FIFO goes below its lower threshold. 0: No interrupt pending 1: Interrupt pending CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 323 Data written to the register is written to the TX FIFO. When reading this register, data from the RX FIFO is read. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 324 0: Interrupt disabled 1: Interrupt enabled TXTHSHDN TX FIFO goes below its lower threshold. 0: Interrupt disabled 1: Interrupt enabled CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 325 RX FIFO underflow 0: Interrupt disabled 1: Interrupt enabled TX FIFO underflow TXUNDERF 0: Interrupt disabled 1: Interrupt enabled SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 326 1: The VCO is powered up. If the LLE is idle, it means the next task starts PRF_CHAN.FREQ quickly if frequency programming is disabled ( 127) CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 327 The value read from the pseudorandom number generator, see Chapter 14. Reading this register causes the shift register to be updated with 13 times rollout. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 328 If set too high, the sensitivity is reduced but sync is not likely to be found on noise. CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 329 01 : Freeze estimate at sync 10 : Peak detect 11 : Continuous before sync, peak detect after sync SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 330 SW6 (0x61FA) – Secondary Sync Word Byte 2 Name Reset Description SYNC_WORD2[23:16] 0x00 Contains bits 23:16 of the secondary synchronization word CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 331 111: 21-dB gain LNA3_CURRENT[1:0] Gain setting, LNA3 00: 0-dB gain (reference level) 01: 3-dB gain 10: 6-dB gain 11: 9-dB gain SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 332 11 : Delayed dc offset estimate used. Delay set by MDMTEST1.DC_DELAY . Until the first estimate is ready, the manual override value is used. CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 333 00 0000: Disabled 00 0001: Enables the temperature sensor (see also the TR0 register description in #IMPLIED).Other values reserved. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 334 00 0000 R/W Controls which observable signal from rf_core is to be muxed out to rfc_obs_sigs(2). See description of RFC_OBS_CTRL0 CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 335 RFRAMCFG (0x61C0) – Radio RAM Configuration Name Reset Description – 0000 1 Reserved Selects active memory page for RF core data memory SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 336 Condition for generating a pulse on radio DMA trigger 1 (DMA trigger 11). RFFDMA0 for the list of conditions. CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 337 RX FIFO area (see Figure 25-1). RFRXFWP RFRXFSWP RFFCFG.RXAUTODEALLOC (and = 1) is incremented by 1 modulo 0x80 unless the write fails. SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 338 25-1) is RFTXFWP RFTXFSWP returned. (and RFFCFG.TXAUTODEALLOC = 1) is incremented by 1 modulo 0x80 unless the write fails. CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 339 BSP_P3 (0x61E3) – CRC Polynomial Byte 3 Name Reset Description 0x00 Bits 31:24 of p register in CRC sub-module P[31:24] SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 340 0x00 BSP_DATA[7:0] BSP_MODE.CP_BUSY When = 0: Write: Provide byte to be processed in coprocessor mode Read: Read processed byte CC2541 Proprietary Mode Radio SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 341 Controls bias current to PA PA_BIAS_CTRL 00: IREF bias 01: IREF and IVREF bias 10: PTAT bias 11: Increased PTAT slope bias SWRU191F – April 2009 – Revised April 2014 CC2541 Proprietary Mode Radio Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 342: Voltage Regulator

    RAM contents are retained while the unregulated 2 V to 3.6 V power supply is present NOTE: The voltage regulator should not be used to provide power to external circuits. Voltage Regulator SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 343: Available Software

    SWRU191F – April 2009 – Revised April 2014 Available Software This chapter presents the various available software solutions relevant to the CC253x, CC2540, and CC2541 family. They are all available free of charge on the TI Web site at www.ti.com/lprf when used with TI LPRF devices.

  • Page 344: Smartrf™ Software For Evaluation (Www.ti.com/Smartrfstudio)

    • No line-of-sight barrier The RemoTI network protocol is Texas Instruments’ implementation of the ZigBee RF4CE standard. It is a complete solution offering hardware and software support for TI’s low-power RF product portfolio. With the RemoTI network protocol we provide: •...

  • Page 345: Simpliciti™ Network Protocol (Www.ti.com/Simpliciti)

    Low data rate and low duty cycle • Ease of use For more information about the SimpliciTI network protocol, see the Texas Instruments SimpliciTI network protocol Web site, www.ti.com/simpliciti. 27.4 TIMAC Software (www.ti.com/timac) TIMAC software is an IEEE 802.15.4 medium-access-control software stack for TI’s IEEE 802.15.4 transceivers and System-on-Chips.

  • Page 346: Z-Stack™ Software (Www.ti.com/Z-Stack)

    • Range of example applications • Multi-role capabilities For more information about TI's BLE stack software, visit Texas Instruments Bluetooth low energy stack software Web site at www.ti.com/blestack. Available Software SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback...

  • Page 347: A Abbreviations

    Error vector magnitude Federal Communications Commission Frame control field Frame check sequence FFCTRL FIFO and frame control FIFO First in, first out SWRU191F – April 2009 – Revised April 2014 Abbreviations Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 348 Phase-locked loop PM1, PM2, Power mode 1, 2, and 3 Power management controller PN7, PN9 7-bit or 9-bit pseudo-random sequence Power-on reset 348 Abbreviations SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...
  • Page 349 Total harmonic distortion Texas Instruments Transmit UART Universal asynchronous receiver/transmitter USART Universal synchronous/asynchronous receiver/transmitter Voltage-controlled oscillator Variable-gain amplifier Watchdog timer XOSC Crystal oscillator SWRU191F – April 2009 – Revised April 2014 Abbreviations Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 350: B Additional Information

    RF transceivers, RF transmitters, RF front ends and System-on-Chips as well as various software solutions for the sub-1 and 2.4-GHz frequency bands. In addition, Texas Instruments provides a large selection of support collateral such as development tools, technical documentation, reference designs, application expertise, customer support, third-party and university programs.

  • Page 351: Texas Instruments Low-Power Rf Web Site

    Texas Instruments Low-Power RF Web Site www.ti.com Texas Instruments Low-Power RF Web Site Texas Instruments’ Low-Power RF Web site has all our latest products, application and design notes, FAQ section, news and events updates, and much more. Just go to www.ti.com/lprf. Low-Power RF Online Community •...

  • Page 352: C References

    6. CC2541 Data Sheet (SWRS110) 7. Bluetooth® Core Technical Specification document, version 4.0 https://www.bluetooth.org/technical/specifications/adopted.htm 8. Universal Serial Bus Revision 2.0 specification http://www.usb.org/developers/docs/usb_20_101111.zip References SWRU191F – April 2009 – Revised April 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 353: Revision History

    NOTE: Page numbers for previous revisions may differ from page numbers in the current version. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. SWRU191F – April 2009 – Revised April 2014 Revision History Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated...

  • Page 354: Important Notice

    IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.
  • Page 355 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments CC2540EMK-USB CC2540EMK...

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