C Clock Generation And Synchronization; Arbitration Procedure Between Two Master Transmitters; Clock Generators During Arbitration - Texas Instruments CC253x User Manual

www.ti.com
20.1.4.3 Arbitration
If two or more master transmitters simultaneously start a transmission on the bus, an arbitration procedure
is invoked. Figure 20-7
uses the data presented on SDA by the competing transmitters. The first master transmitter that generates
a logic high is overruled by the opposing master generating a logic low. The arbitration procedure gives
priority to the device that transmits the serial data stream with the lowest binary value. The master
transmitter that lost arbitration switches to the slave receiver mode. If two or more devices send identical
first bytes, arbitration continues on the subsequent bytes.
Bus Line
SCL
Data From
Device #1
Data From
Device #2
Bus Line
SDA
Figure 20-7. Arbitration Procedure Between Two Master Transmitters
2
20.1.5 I

C Clock Generation and Synchronization

2
The I C clock SCL is provided by the master on the I
serial clock generator generates the SCL clock from the system clock. The serial clock generator is
switched off when the I
The frequency of the SCL is determined by the system clock frequency and the division factor given by
the I2CCFG.CRx bits. Example frequencies for a 32-MHz system clock are given in the I2CCFG register
description.
During the arbitration procedure, the clocks from the different masters must be synchronized. A device
that first generates a low period on SCL overrules the other devices, forcing them to start their own low
periods. SCL is then held low by the device with the longest low period. The other devices must wait for
SCL to be released before starting their high periods.
allows a slow slave to slow down a fast master.
Figure 20-8. Synchronization of Two I
SWRU191F – April 2009 – Revised April 2014
Submit Documentation Feedback
shows the arbitration procedure between two devices. The arbitration procedure
1
1
1
2
C module is in slave mode.
SCL From
Device #1
SCL From
Device #2
Bus Line
SCL
Copyright © 2009–2014, Texas Instruments Incorporated
Device #1 Lost Arbitration
and Switches Off
n
0 0
1
0 0
1
2
C bus. When the I
Figure 20-8 shows the clock synchronization. This
Wait
Start HIGH
State
Period
2
C Clock Generators During Arbitration
0
1
0
1
2
C module is in master mode, the
Operation
177
2
I C