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Texas Instruments TPS543620 Converter Manuals
Manuals and User Guides for Texas Instruments TPS543620 Converter. We have
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Texas Instruments TPS543620 Converter manual available for free PDF download: User Manual
Texas Instruments TPS543620 User Manual (38 pages)
SWIFT Step-Down Converter Evaluation Module
Brand:
Texas Instruments
| Category:
Motherboard
| Size: 3 MB
Table of Contents
Table of Contents
1
1 Introduction
3
Background
3
Before You Begin
3
Table 1-1. Input Voltage and Output Current
3
Performance Characteristics Summary
4
Table 1-2. TPS543620EVM Small Size (U1) Performance Characteristics Summary
4
Table 1-3. TPS543620EVM High Efficiency (U2) Performance Characteristics
5
2 Configurations and Modifications
6
Output Voltage
6
Table 2-1. VOUT Selection
6
Switching Frequency (FSEL Pin)
7
Current Limit, Soft-Start Time, and Internal Compensation (MODE Pin)
7
Adjustable UVLO
7
Table 2-2. FSEL Selection
7
Table 2-3. MODE Selection
7
3 Test Setup and Results
8
Input/Output Connections
8
Table 3-1. Connectors and Jumpers
9
Table 3-2. Test Points
10
Efficiency
11
Table 3-3. Efficiency Measurement Test Points
11
Output Voltage Regulation
14
Figure 3-6. U1 Load Regulation
14
Figure 3-7. U1 Line Regulation
14
Figure 3-8. U2 Load Regulation
14
Figure 3-9. U2 Line Regulation
14
Load Transient and Loop Response
15
Figure 3-10. U1 Transient Response
15
Figure 3-11. U2 Transient Response
15
Figure 3-12. U1 Bode Plot
15
Figure 3-13. U2 Bode Plot
15
Figure 3-14. U2 Loop Gain with Different Ramp Settings
16
Figure 3-15. U2 Loop Phase with Different Ramp Settings
16
Output Voltage Ripple
17
Figure 3-16. U1 Output Ripple - no Load
17
Figure 3-17. U1 Output Ripple - 6-A Load
17
Figure 3-18. U2 Output Ripple - no Load
17
Figure 3-19. U2 Output Ripple - 6-A Load
17
Input Voltage Ripple
18
Figure 3-20. U1 Input Ripple - no Load
18
Figure 3-21. U1 Input Ripple - 6-A Load
18
Figure 3-22. U2 Input Ripple - no Load
18
Figure 3-23. U2 Input Ripple - 6-A Load
18
Synchronizing to a Clock
19
Figure 3-24. U1 and U2 Synchronized to a Clock
19
Figure 3-25. U2 Clock Synchronization Transitions
19
Start-Up and Shutdown with en
20
Figure 3-26. U2 Start-Up with en - no Load
20
Figure 3-27. U2 Shutdown with en - no Load
20
Figure 3-28. U2 Start-Up with en - 0.2-Ω Load
20
Figure 3-29. U2 Startup with en - no Load and Measuring BP5
20
Start-Up and Shutdown with VIN
21
Figure 3-30. U2 Start-Up with VIN - 0.3-Ω Load
21
Figure 3-31. U2 Shutdown with VIN - 0.3-Ω Load
21
Start-Up into Pre-Bias
22
Figure 3-32. U2 Start-Up into 0.5-V Pre-Bias
22
Hiccup Current Limit
23
Figure 3-33. U2 Output Overcurrent Protection - Overload with High Limit
23
Figure 3-34. U2 Output Overcurrent Protection - Overload with Low Limit
23
Figure 3-35. U2 Output Overcurrent Protection - Short with Low Limit
23
Figure 3-36. U2 OCP Hiccup and Recover - High Limit
23
Overvoltage Protection
24
Figure 3-37. U2 Overvoltage Protection
24
Figure 3-38. U2 OVP and Recover
24
Thermal Performance
25
Figure 3-39. U1 Thermal Performance - 6-A Load and U2 off
25
Figure 3-40. U2 Thermal Performance - 6-A Load and U1 off
25
Figure 3-41. U1 Thermal Performance - both 6-A Load
25
Figure 3-42. U2 Thermal Performance - both 6-A Load
25
4 Board Layout
26
Layout
26
Figure 4-1. Top-Side Composite View
26
Figure 4-2. Bottom-Side Composite View (Viewed from Bottom)
26
5 Schematic and Bill of Materials
27
Figure 4-3. Top Layer Layout
27
Figure 4-4. MID Layer 1 Layout
27
Figure 4-5. MID Layer
27
Figure 4-6. Bottom Layer Layout
27
Figure 5-1. U1 Schematic
28
Schematic
28
Figure 5-2. U2 Schematic
29
Bill of Materials
30
Table 5-1. TPS543620EVM Bill of Materials
30
6 Revision History
31
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