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1.3.4
Adjustable UVLO
The undervoltage lockout (UVLO) can be adjusted externally using R3 and R4. The EVM is set for a start
voltage of 5.34 V and stop voltage of 4.31 V using R3 = 221 kΩ and R4 = 59.0 kΩ. Use
Equation 6
to calculate the required resistor values for R3 and R4 respectively for different start and stop
voltages. The typical values of the constants in the two equations are as follows: V
1.21 V, I
= 1.8 µA, and I
EN_pup
R
UVLO_ H
I
EN _ pup
R
UVLO_ L
V
STOP
1.3.5
Input Voltage Rails
The EVM is designed to accommodate different input voltage levels for the power stage and control logic.
During normal operation, the VIN inputs are the same with R11 shorted. The single input voltage is
supplied to J6. If desired, the two input voltage rails may be separated by removing R11. The control logic
input voltage can be supplied to J4 and the power stage input voltage to J6.
1.3.6
Further Modification
Be aware, changing the input and output of conditions of the EVM will impact the design. It may also be
necessary to modify the inductor, output capacitor and compensation components for the desired
performance in the application. Additionally the CSD86330Q3D power block limits the output voltage to a
maximum recommend output voltage of 22 V. Please see the data sheet or the excel design spreadsheet
located in the product folder for details.
2
Test Setup and Results
This section describes how to properly connect, set up, and use the EVM. The section also includes test
results typical for the EVM covering efficiency, output voltage regulation, load transients, loop response,
output ripple, input ripple, start up and shutdown.
2.1
Input/Output Connections
This EVM includes input/output connectors and test points as shown in
of supplying at least 6 A must be connected to J6 through a pair of 20-AWG wires. The load must be
connected to J2 through a pair of 20-AWG wires. The maximum load-current capability must be 2 A. Wire
lengths must be minimized to reduce losses in the wires. If any modification is done to the EVM design, an
input supply and load rated for the new design are required. Test point TP8 provides a place to monitor
the V
input voltages with TP9 providing a convenient ground reference. TP3 is used to monitor the output
IN
voltage with TP4 as the ground reference.
Reference Designator
J1
2-pin header for V
J2
V
J3
2-pin header for GND connections
J4
2-pin header for optional V
J5
2-pin header for V
J6
V
J7
2-pin header for GND connections
JP1
3-pin header for EN jumper. Install jumper from pins 1-2 to enable or pins 2-3 to disable.
SLVU799A – November 2012 – Revised March 2013
Submit Documentation Feedback
= 3.2 µA.
EN_hys
§
·
V
EN _ DIS
u ¨
¸
V
V
¨
¸
START
STOP
V
©
¹
EN _ ON
§
·
V
EN _ DIS
u ¨
¸
1
I
¨
¸
EN _ hys
V
©
¹
EN _ ON
R
u
V
UVLO_ H
EN _ DIS
V
R
EN _ DIS
UVLO _ H
Table 3. EVM Connectors and Test points
voltage connections
OUT
, 15 V at 2-A maximum
OUT
input voltage connections (see
BIAS
input voltage connections
IN
(see
Table 1
for V
range)
IN
IN
Copyright © 2012–2013, Texas Instruments Incorporated
I
I
u
EN _ pup
EN _ hys
Function
Section 1.3.5
Using the TPS43061 Boost Evaluation Module (EVM)
Test Setup and Results
Equation 5
= 1.14 V, V
EN_DIS
Table
3. A power supply capable
)
and
=
EN_ON
(5)
(6)
5
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