System Controller; Cpu Bus Interface - Motorola MVME5500 Installation And Use Manual

Functional Description

System Controller

4

CPU Bus Interface

4-4
MVME5500 provides 1.5V as the SRAM I/O voltage. The L3 bus operates
at 200 MHz.
The GT-64260B system controller for PowerPC architecture processors is
a single chip solution that provides the following features:
A 64-bit interface to the CPU bus
A 64-bit SDRAM interface
A 32-bit generic device interface for Flash, etc.
Two 64-bit, 66 MHz PCI bus interfaces
Three 10/100Mb Ethernet MAC ports (two ports not used)
A DMA engine for moving data between the buses
An interrupt controller
An I2C device controller
PowerPC bus arbiter
Counter/timers
Watchdog timer
Each of the device buses are de-coupled from each other, enabling
concurrent operation of the CPU bus, PCI buses, and access to SDRAM.
Refer to the GT-64260B System Controller for PowerPC Processors Data
Sheet, listed in Appendix D, Related
The GT-64260B supports MPX or 60x bus mode operation. The
MVME5500 board has jumper/build option resistors to select either
operating mode at power-up.
Documentation, for more details.
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