Functional Description; Ppc Bus Interface; Ppc Map Decoders; Table 2-1. Chrp Compliant Memory Map - Motorola MTX Series Programmer's Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller

Functional Description

2

PPC Bus Interface

PPC Map Decoders

2-4
The PPC Bus Interface is designed to be coupled directly to up to two PPC
microprocessors as well as a memory/cache subsystem. It uses a subset of
the capabilities of the PPC bus protocol.
The Raven address decoders have been designed to be as flexible as
possible to provide a wide range of addressing possibilities. There are five
address map decoders in the Raven which determine the PPC bus
addresses to which the Raven will respond: the PPC Register File Decoder,
and four programmable decoders.
compliant memory map. (Another similar map is shown in

Table 2-1. CHRP Compliant Memory Map

PPC Address
$00000000-$7FFFFFFF
$80000000-$FCFFFFFF
$FD000000-$FDFFFFFFF ISA Memory (16M)
$FE000000-$FE7FFFFF
$FE800000-$FEBFFFFF
$FEC00000-$FEF7FFFF
$FEF80000-$FEF8FFFF
$FEF90000-$FEF9FFFF
$FEFA0000-$FEFAFFFF
$FEFB0000-$FEFBFFFF
$FEFC0000-$FEFEFFFF
$FEFF0000-$FEFFFFFF
$FF000000-$FFFFFFFF
Table 2-1 shows a typical CHRP
Function
System Memory (2G)
PCI Memory (2G - 48M)
Discontiguous PCI IO (8M)
Contiguous PCI IO (4M)
reserved (3.5M)
Falcon 0 Registers (64K)
Falcon 1 Registers (64K)
Falcon 2 Registers (64K)
Falcon 3 Registers (64K)
reserved (192K)
Raven Registers (64K) (EXT00 => 0)
System ROM/Flash (16MB)
Computer Group Literature Center Web Site
Table 1-3.)