System Memory; Serial Presence Detect (Spd) Definitions; Hawk Asic; Hawk I2C Interface And Configuration Information - Motorola MVME5100 Programmer's Reference Manual

Product Data and Memory Maps
1

System Memory

Serial Presence Detect (SPD) Definitions

Hawk ASIC

2
Hawk I C interface and configuration information
1-6
MVME5100 system memory characteristics are fully compatible with
those of the Hawk ASIC for memory Blocks A, B, C, and E.
The on-board memory Blocks are Blocks A and B. The optional add-on
mezzanine memory Blocks are C (first mezzanine attached) and
E (second mezzanine attached).
The MVME5100 SPD uses the SPD JEDEC standard definition. On board
SPD for SDRAM Bank A or both A and B of the Hawk shall be accessed
at Address $A8 . Only Bank A or Banks A and B will be populated. If both
banks A and B are populated, they will be the same speed and memory
size. Memory Mezzanine 1 SPD for SDRAM Bank C of the Hawk shall be
accessed at Address $AA. Memory Mezzanine 2 SPD for SDRAM Bank
E of the Hawk shall be accessed at address $AC.
The Hawk ASIC has an I
interface bus: Serial Clock Line (SCL) and Serial Data Line (SDA)
composed of two 256 x 8 Serial EEPROM's.
This interface has master-only capability and is used to communicate the
configuration information to a slave I
EEPROM is used to maintain the configuration information related to the
board (Vital Product Data, User configuration Data, etc.) and a seperate
EEPROM is used for on-board Memory Subsystem Data (MSD).
If a optional memory mezzanine is used, that mezzanine shall contain a
seperate EEPROM with its own memory subsystem data. Each slave
device connected to the I
address.
2
C (Inter-Integrated Circuit) two-wire serial
2
C serial EEPROM. A seperate
2
C bus is software addressable by a unique
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