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Freescale Semiconductor, Inc.
3.4
Programming the slave QUICC
The slave QUICC (core disabled) provides the following functions on the M68360QUADS-040:
1. DRAM Controller
2. Chip Select and DSACK~ generator.
3. Parallel port (ADI).
4. UART for terminal or host computer connection.
5. Dual Ethernet controller.
6. Interrupter
7. Serial EEPROM interface.
8. General Purpose I/O signals.
The slave QUICC internal registers must be programmed after hardware reset as described in the following
paragraphs. The addresses and programming values are in hexadecimal base.
Please refer to the MC68360 QUICC User's Manual for more information.
3.4.1
Module Base Address Register
The slave QUICC's module base address register (MBAR) controls the location of its internal memory and
registers and their access space. The slave QUICC MBAR resides at a fixed location in '0003FF00' in the
CPU space.
The MBAR must be initialized to '00122001' to obtain the memory map as described in TABLE 3-2
3.4.2
Module Configuration Register
The module configuration register (MCR) controls the SIM60 configuration in the slave QUICC. The MCR
is initialized to 60018C3F after reset.
3.4.3
CLKO Control Register
The CLKO control register (CLKOCR) controls the operation of the CLKO(1:2) pins. This register must be
initialized to '03' after reset to enable CLKO2 and disable CLKO1.
3.4.4
PLL Control Register
The PLL control register (PLLCR) controls the operation of the PLL. There is no need to program the
PLLCR after hard reset, because the configuration of the MODCK(0:1) pins on the QUADS determines its
value. It is recommended to set the PLLWR bit to prevent accidental writing.
3.4.5
Port E Pin Assignment Register
Port E pins can be programmed by the port E pin assignment register (PEPAR). The PEPAR must be
initialized to '37C0' to configure Port E of the slave QUICC as follows:
•
The output of the slave QUICC interrupt request is on IOUT(0:2)~ pins.
•
RAS1~ and RAS2~ double drive function is used to drive the DRAM.
•
The A(31:28) pins of the slave QUICC are configured as write enables.
•
The OE~/AMUX pin is configured as AMUX to drive the external multiplexers of the DRAM.
•
The CAS(0:3)~ output function is used for the DRAM.
•
CS7~ output function is enabled.
•
AVECO~ function is chosen.
3.4.6
System Protection Control
The system protection register (SYPCR) controls the system monitors, the software watchdog, and the bus
monitor timing. This register must be initialized to '34' to disable the software watchdog, disable the double
M68360QUADS-040 Hardware User's Manual
For More Information On This Product,
Go to: www.freescale.com
OPERATING INSTRUCTIONS
21
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