Pci Local Bus Memory Map; Table 2-1. Processor Default View Of The Memory Map - Motorola MVME2603-1121A Installation And Use Manual

Memory Maps
2
Processor Address
Start
00000000
80000000
80020000
FEF80000
FEF90000
FEFF0000
FF000000
FFF00000

PCI Local Bus Memory Map

2-6

Table 2-1. Processor Default View of the Memory Map

End
7FFFFFFF 2GB
8001FFFF 128KB
FEF7FFFF 2GB-16MB-640KB
FEF8FFFF 64KB
FEFEFFFF 384KB
FEFFFFFF 64KB
FFEFFFFF 15MB
FFFFFFFF 1MB
Notes 1. Default map for PCI/ISA I/O space. Allows software to
determine whether the system is MPC105-based or
Falcon/Raven-based by examining either the PHB Device ID or
the CPU Type register.
2. The first 1MB of ROM/Flash bank A (soldered 4MB or 8MB
ROM/Flash) appears in this range after a reset if the rom_b_rv
control bit in the FalconÕs ROM B Base/Size register is cleared.
If the rom_b_rv control bit is set, this address range maps to
ROM/Flash bank B (socketed 1MB ROM/Flash).
For detailed processor memory maps, including suggested CHRP-
and PREP-compatible memory maps, refer to the MVME2600 Series
Single Board Computer ProgrammerÕs Reference Guide (part number
V2600A/PG).
The PCI memory map is controlled by the Raven MPU/PCI bus
bridge controller ASIC and by the Universe PCI/VME bus bridge
ASIC. The Raven and Universe devices adjust system mapping to
suit a given application via programmable map decoder registers.
No default PCI memory map exists. Resetting the system turns the
PCI map decoders off, and they must be reprogrammed in software
for the intended application.
Size DeÞnition
Not Mapped
PCI/ISA I/O Space
Not Mapped
Falcon Registers
Not Mapped
Raven Registers
Not Mapped
ROM/Flash Bank A or Bank B
Notes
1
2