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MC68302 Applications
CLKO
AS
DTACK
DONE
NOTE: If the byte count had reached zero, DONE would be asserted by the IDMA, indicating normal transfer termination.
Figure D-8. Typical IDMA External Cycles Showing Block Transfer Termination
Operation
Done Not Synchronized—DONE is asserted as an input
during the first access of an 8-bit peripheral when operat-
ing with 1 6-bit memory.
Bus Error Source—A bus error occurred during the read
portion of an IDMA cycle.
Bus Error Destination—A bus error occurred during the
write portion of an IDMA cycle.
Normal Channel Transfer Done—The BCR decremented
to zero or the external peripheral asserted DONE and no
errors occurred during any IDMA cycle.
* These bits are cleared by writing a one or setting RST in the CMR.
Figure D-9 depicts the typical cycles used on a 16-bit bus when the source data size and
destination data size are not equal. In this example, the source size is byte and the destina-
tion size is word. The IDMA performs two read cycles to obtain data and then performs a
write cycle to place data into the destination location. If the CMR SAPI bit was set, then each
byte read increments the SAPR by two. Hence, the SAPR is always pointing to the leftmost
or rightmost byte of the 16-bit bus. This type of transfer duplicates the function of an M68000
MOVEP instruction.
CLKO
AS
(OUTPUT)
DTACK
DACK
(OUTPUT)
BGACK
Figure D-9. Typical IDMA Source to Word Destination IDMA Cycles
D-28
READ CYCLE
S0
S1
S2
S3
S4
Table D-3. Channel Status Register Bits
READ 1
MC68302 USER'S MANUAL
S5
S6
S7
Bit
7
6
DNS
BES
Reserved
BED
DONE
READ 2
WRITE CYCLE
5
4
3
2
1
1*
1*
WRITE
MOTOROLA
OUTPUT
I/O
INPUT
1
0
1*
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