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3.5.2.4 TIMER COUNTER (TCN1, TCN2).
TCN1 and TCN2 are 16-bit up-counters.
Each is memory-mapped and can be read by the user. A read cycle to TCN 1
and TCN2 yields the current value of the timer and does not affect the count-
ing operation.
When working in the MC68008 mode (BUSW is low), reading the high byte
of TCN1 and TCN2 will latch the low byte into a temporary register; a sub-
sequent read cycle on the low byte yields the value of the temporary register.
A write cycle to TCN1 and TCN2 causes it and the corresponding prescaler
to be reset. In MC68008 mode (BUSW is low), a write cycle to either the high
or low byte will reset the respective counter and the prescaler.
3.5.2.5 TIMER EVENT REGISTERS (TER1, TER2).
Each TER is an 8-bit register used
to report events recognized by any of the timers. On recognition of an event,
the timer will set the appropriate bit in the TER, regardless of the corre-
sponding interrupt enable bits (ORI and CE) in the TMR. TER1 and TER2,
which appear to the user as memory-mapped registers, may be read at any
time.
A bit is reset by writing a one to that bit (writing a zero does not affect a bit's
value). More than one bit may be reset at a time. Both bits must be reset
before the timer will negate the INRQ to the interrupt controller. This register
is cleared by reset.
RESERVED
REF
I
CAP
CAP - Capture Event
The counter value has been latched into the TCR. The CE bits in the TMR
are used to enable the interrupt request caused by this event.
REF - Output Reference Event
The counter has reached the TRR value. The ORI bit in the TMR is used to
enable the interrupt request caused by this event.
Bits 7-2 - Reserved for future use.
3.5.3 Watchdog Timer
3-38
A watchdog timer is used to protect against system failures by providing a
means to escape from unexpected input conditions, external events, or pro-
MC68302 USER'S MANUAL
MOTOROLA
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