Gestetner A265 Service Manual page 519

HARDWARE OVERVIEW
1. Image input circuit
CPU: UPD705101GM
• Sequence control for the image input circuit
• Clock/time control
• DMA control
ASIC: UPD65842
• Stores the image data from the BICU board in the main machine into the
buffer memory (DRAM)
• Address control when recalling the data from the memory
• DMA control for the network interface circuit
DRAM:
Compresses and stores the image data from the main machine (Total 16 MB.
9MB for work area, 4MB for buffer area, 3 MB for the working program)
Flash ROM:
Contains the scanner controller program and stores the UP/SP settings for
the scanner (2 MB)
2. Network interface circuit
CPU: MC58340VP
• Sequence control for the network interface circuit
• Clock/time control
• DMA control
ASIC (DISCII):
• Bus interface between the image input circuit and network interface circuit
Bridge: AG1001V
This is an ISA-PCI bridge; it corrects the timing and decodes the commands
between the ISA bus and the PCI bus.
MAC: AM79C971
This is a LAN controller; it covers the same functions as the Data Link Layer
of the OSI model.
PHY: This device covers the same functions as the Physical Layer of the OSI
model.
Flash ROM: Contains the program for the network interface (2 MB)
EEPROM: Contains UP/SP settings for the network interface
A265/A267
CÓPIA NÃO CONTROLADA
18-4
CÓPIA NÃO CONTROLADA
SM