HP 64782 User Manual page 208

Emulation Analyzer Trace Signals
Trace Analyzer
Signals Channel #
bit 8 ch 56
bit 9 ch 57
bit 10 ch 58
bit 11 ch 59
bit 12 ch 60
bit 13 ch 61
bit 14 ch 62
bit 15 ch 63
Signal Signal
Name Description
DSACK0 These are processor DSACK signals, which may be
DSACK1 configured as I/O pins.
BERR 0 = bus error
1 = no bus error
HALT 0 = processor halt
1 = processor is not halted
CODE 0 = instruction fetch
1 = data transfer
FLUSH 0 = first instruction fetch following any program
transfer
1 = no program transfer
LOWBYTE These are translation RAM signals which describe the
HIBYTE bus cycle.
15:14
0:0 use SIZ1, SIZ0 bits (status bits 6:5)
0:1 low-byte transfer
1:0 high-byte transfer
1:1 word transfer
Using the Emulation Analyzer
To position the trace display on screen
207