HP 64782 User Manual page 125

Configuring the Emulator
To display information about chip selects
The following table reflects the current values in the sim (processor)
register set.
Select Assign Base
------ ------ ------- ---- ----- ----- ----- ---- ------ ----- ------ ----
CSBOOT 16-bit 000000H 1M
CS0 16-bit 000000H 2K
CS1 16-bit 000000H 2K
CS2 16-bit 000000H 2K
CS3 16-bit 000000H 2K
CS4 16-bit 000000H 2K
CS5 16-bit 000000H 2K
CS6 16-bit 000000H 2K
CS7 16-bit 000000H 2K
CS8 16-bit 000000H 2K
CS9 16-bit 000000H 2K
CS10 16-bit 000000H 2K
To display information about chip selects from the emsim (emulator) register
set, choose Display→Configuration Info→Chip Selects (Emulator
SIM) from either the configuration interface the emulator/analyzer interface
pulldown menu.
The following table reflects the current values in the emsim register set.
These values will be loaded into the processor when the monitor is
entered from emulation reset.
Select Assign Base
------ ------ ------- ---- ----- ----- ----- ---- ------ ----- ------ ----
CSBOOT 16-bit 060000H 128K async both
CS0 16-bit 000000H 64K
CS1 16-bit 000000H 64K
CS2 16-bit 000000H 64K
CS3 16-bit 000000H 2K
CS4 16-bit 000000H 2K
CS5 16-bit FFE800H 64K
CS6 16-bit 080000H 128K async lower both
CS7 16-bit 080000H 128K async upper both
CS8 16-bit 010000H 64K
CS9 16-bit 010000H 64K
CS10 16-bit 010000H 64K
124
Size Mode Byte R/W
async both both
async off rsvd
async off rsvd
async off rsvd
async off rsvd
async off rsvd
async off rsvd
async off rsvd
async off rsvd
async off rsvd
async off rsvd
async off rsvd
Size Mode Byte R/W
read
async upper write AS
async lower write AS
async both read
async off rsvd
async off rsvd
async both both
async both read
async lower write AS
async upper write AS
Strb DSACK Space IPL
AS 13wait s/u all
AS 0wait cpu all
AS 0wait cpu all
AS 0wait cpu all
AS 0wait cpu all
AS 0wait cpu all
AS 0wait cpu all
AS 0wait cpu all
AS 0wait cpu all
AS 0wait cpu all
AS 0wait cpu all
AS 0wait cpu all
Strb DSACK Space IPL
AS 2wait s/u all
0wait s/u level4 off
0wait s/u level7 off
AS 0wait s/u level7 off
AS 0wait cpu all
AS 0wait cpu all
AS 0wait s/u level7 on
AS 3wait s/u all
AS 3wait s/u all
AS 1wait s/u all
0wait s/u all
0wait s/u all
AVEC
off
off
off
off
off
off
off
off
off
off
off
off
AVEC
off
off
off
off
off
off
off
off