Settling Time Requirements; Figure 6.4. Adc0 Equivalent Input Circuits - Silicon Laboratories C8051F120 Manual

6.2.3. Settling Time Requirements

When the ADC0 input configuration is changed (i.e., a different MUX or PGA selection is made), a minimum track-
ing time is required before an accurate conversion can be performed. This tracking time is determined by the ADC0
MUX resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the
conversion. Figure 6.4 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes.
Notice that the equivalent time constant for both input circuits is the same. The required settling time for a given set-
tling accuracy (SA) may be approximated by Equation 6.1. When measuring the Temperature Sensor output, R
reduces to R . An absolute minimum settling time of 1.5 µs is required after any MUX or PGA selection. Note
MUX
that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion. For most
applications, these three SAR clocks will meet the tracking requirements.
Equation 6.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R is the sum of the ADC0 MUX resistance and any external source resistance.
TOTAL
n is the ADC resolution in bits (10).
Differential Mode
MUX Select
AIN0.x
R
MUX
RC = R * C
Input MUX SAMPLE
AIN0.y
R
MUX
MUX Select
n
2
 
------ - ×
t = ln
 
SA

Figure 6.4. ADC0 Equivalent Input Circuits

= 5k
C = 10pF
SAMPLE
C = 10pF
SAMPLE
= 5k
C8051F120/1/2/3/4/5/6/7
R C
TOTAL SAMPLE
Single-Ended Mode
MUX Select
AIN0.x
RC = R
Input MUX
Rev. 1.2
TOTAL
R = 5k
MUX
C = 10pF
SAMPLE
* C
SAMPLE
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