Figure 18.1. Emi0Cn: External Memory Interface Control; Figure 18.2. Emi0Cf: External Memory Configuration - Silicon Laboratories C8051F120 Manual

Figure 18.1. EMI0CN: External Memory Interface Control

R/W R/W
PGSEL7 PGSEL6 PGSEL5
Bit7 Bit6
Bits7-0: PGSEL[7:0]: XRAM Page Select Bits.
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when
using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM.
0x00: 0x0000 to 0x00FF
0x01: 0x0100 to 0x01FF
...
0xFE: 0xFE00 to 0xFEFF
0xFF: 0xFF00 to 0xFFFF

Figure 18.2. EMI0CF: External Memory Configuration

R/W R/W
- - PRTSEL
Bit7 Bit6
Bits7-6: Unused. Read = 00b. Write = don't care.
Bit5: PRTSEL: EMIF Port Select.
0: EMIF active on P0-P3.
1: EMIF active on P4-P7.
Bit4: EMD2: EMIF Multiplex Mode Select.
0: EMIF operates in multiplexed address/data mode.
1: EMIF operates in non-multiplexed mode (separate address and data pins).
Bits3-2: EMD1-0: EMIF Operating Mode Select.
These bits control the operating mode of the External Memory Interface.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to on-chip
memory space.
01: Split Mode without Bank Select: Accesses below the 8k boundary are directed on-chip. Accesses
above the 8k boundary are directed off-chip. 8-bit off-chip MOVX operations use the current contents
of the Address High port latches to resolve upper address byte. Note that in order to access off-chip
space, EMI0CN must be set to a page that is not contained in the on-chip address space.
10: Split Mode with Bank Select: Accesses below the 8k boundary are directed on-chip. Accesses
above the 8k boundary are directed off-chip. 8-bit off-chip MOVX operations use the contents of
EMI0CN to determine the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to the CPU.
Bits1-0: EALE1-0: ALE Pulse-Width Select Bits (only has effect when EMD2 = 0).
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
R/W R/W R/W
PGSEL4 PGSEL3
Bit5 Bit4 Bit3
R/W R/W R/W
EMD2 EMD1
Bit5 Bit4 Bit3
Rev. 1.2
C8051F120/1/2/3/4/5/6/7
R/W R/W
PGSEL2 PGSEL1 PGSEL0
Bit2 Bit1
SFR Address:
R/W R/W
EMD0 EALE1 EALE0
Bit2 Bit1
SFR Address:
SFR Page:
R/W Reset Value
00000000
Bit0
0xA2
SFR Page: 0
R/W Reset Value
00000011
Bit0
0xA3
0
201