Figure 15.9. Pll0Mul: Pll Clock Scaler Register; Figure 15.10. Pll0Flt: Pll Filter Register - Silicon Laboratories C8051F120 Manual

Figure 15.9. PLL0MUL: PLL Clock Scaler Register

R/W R/W
PLLN7 PLLN6 PLLN5
Bit7 Bit6
Bits 7-0: PLLN7-0: PLL Multiplier.
These bits select the multiplication factor of the divided PLL reference clock. When set to any non-
zero value, the multiplication factor will be equal to the value in PLLN7-0. When set to '00000000b',
the multiplication factor will be equal to 256.
R/W R/W
- - PLLICO1 PLLICO0
Bit7 Bit6
Bits 7-6: UNUSED: Read = 00b; Write = don't care.
Bits 5-4: PLLICO1-0: PLL Current-Controlled Oscillator Control Bits.
Selection is based on the desired output frequency, according to the following table:
PLL Output Clock
65 - 100 MHz
45 - 80 MHz
30 - 60 MHz
25 - 50 MHz
Bits 3-0: PLLLP3-0: PLL Loop Filter Control Bits.
Selection is based on the divided PLL reference clock, according to the following table:
Divided PLL Reference Clock
19 - 30 MHz
12.2 - 19.5 MHz
7.8 - 12.5 MHz
5 - 8 MHz
R/W R/W R/W
PLLN4 PLLN3
Bit5 Bit4 Bit3

Figure 15.10. PLL0FLT: PLL Filter Register

R/W R/W R/W
PLLLP3
Bit5 Bit4 Bit3
C8051F120/1/2/3/4/5/6/7
R/W R/W
PLLN2 PLLN1
Bit2 Bit1
R/W R/W
PLLLP2 PLLLP1
Bit2 Bit1
PLLICO1-0
00
01
10
11
PLLLP3-0
0001
0011
0111
1111
Rev. 1.2
R/W Reset Value
PLLN0 00000001
Bit0
SFR Address: 0x8E
SFR Page: F
R/W Reset Value
PLLLP0 00110001
Bit0
SFR Address: 0x8F
SFR Page: F
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