Table 14.1.Reset Electrical Characteristics - Silicon Laboratories C8051F120 Manual

C8051F120/1/2/3/4/5/6/7
-40°C to +85°C unless otherwise specified.
PARAMETER
/RST Output Low Voltage
/RST Input High Voltage
/RST Input Low Voltage
/RST Input Leakage Current
VDD for /RST Output Valid
AV+ for /RST Output Valid
VDD POR Threshold (V
RST
Minimum /RST Low Time to
Generate a System Reset
Reset Time Delay
Missing Clock Detector Timeout
172
Table 14.1. Reset Electrical Characteristics
CONDITIONS
I = 8.5 mA, VDD = 2.7 V to 3.6 V
OL
/RST = 0.0 V
)
/RST rising edge after VDD crosses
V threshold
RST
Time from last system clock to reset
initiation
Rev. 1.2
MIN TYP MAX UNITS
0.6
0.7 x
VDD
0.3 x
VDD
50
1.0
1.0
2.40 2.55 2.70
10
80 100 120
100 220 500
V
V
µA
V
V
V
ns
ms
µs