Figure 19.8. Xbr1: Port I/O Crossbar Register 1 - Silicon Laboratories C8051F120 Manual

Figure 19.8. XBR1: Port I/O Crossbar Register 1

R/W R/W
SYSCKE T2EXE
Bit7 Bit6
Bit7: SYSCKE: /SYSCLK Output Enable Bit.
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK (divided by 1, 2, 4, or 8) routed to Port pin. divide factor is determined by the
CLKDIV1-0 bits in register CLKSEL (See
Bit6: T2EXE: T2EX Input Enable Bit.
0: T2EX unavailable at Port pin.
1: T2EX routed to Port pin.
Bit5: T2E: T2 Input Enable Bit.
0: T2 unavailable at Port pin.
1: T2 routed to Port pin.
Bit4: INT1E: /INT1 Input Enable Bit.
0: /INT1 unavailable at Port pin.
1: /INT1 routed to Port pin.
Bit3: T1E: T1 Input Enable Bit.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
Bit2: INT0E: /INT0 Input Enable Bit.
0: /INT0 unavailable at Port pin.
1: /INT0 routed to Port pin.
Bit1: T0E: T0 Input Enable Bit.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
Bit0: CP1E: CP1 Output Enable Bit.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
R/W R/W R/W
T2E INT1E T1E
Bit5 Bit4 Bit3
Section "15. OSCILLATORS" on page
Rev. 1.2
C8051F120/1/2/3/4/5/6/7
R/W R/W
INT0E T0E CP1E
Bit2 Bit1
SFR Address:
R/W Reset Value
00000000
Bit0
0xE2
SFR Page: F
173).
225