Figure 12.18. Psw: Program Status Word - Silicon Laboratories C8051F120 Manual

C8051F120/1/2/3/4/5/6/7
R/W R/W
CY AC
Bit7 Bit6
Bit7: CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtrac-
tion). It is cleared to 0 by all other arithmetic operations.
Bit6: AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from
(subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations.
Bit5: F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
Bits4-3: RS1-RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
RS1
0
0
1
1
Bit2: OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases.
Bit1: F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
Bit0: PARITY: Parity Flag.
This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even.
144

Figure 12.18. PSW: Program Status Word

R/W R/W
F0 RS1
Bit5 Bit4
RS0 Register Bank
0 0
1 1
0 2
1 3
Rev. 1.2
R/W R/W R/W
RS0 OV F1
Bit3 Bit2 Bit1
Address
0x00 - 0x07
0x08 - 0x0F
0x10 - 0x17
0x18 - 0x1F
R Reset Value
PARITY 00000000
Bit
Bit0
Addressable
SFR Address: 0xD0
SFR Page: All Pages