Figure 5.7. Adc0Cf: Adc0 Configuration Register - Silicon Laboratories C8051F120 Manual

C8051F120/1/2/3/4/5/6/7

Figure 5.7. ADC0CF: ADC0 Configuration Register

0
SFR Page:
0xBC
SFR Address:
R/W R/W
AD0SC4 AD0SC3
Bit7 Bit6
Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits.
The SAR Conversion clock is derived from system clock by the following equation, where AD0SC
refers to the 5-bit value held in AD0SC4-0, and CLK
(Note: the ADC0 SAR Conversion Clock should be less than or equal to 2.5 MHz).
AD0SC =
When the AD0SC bits are equal to 00000b, the SAR Conversion clock is equal to SYSCLK to facili-
tate faster ADC conversions at slower SYSCLK speeds.
Bits2-0: AMP0GN2-0: ADC0 Internal Amplifier Gain (PGA).
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5
56
R/W R/W
AD0SC2 AD0SC1 AD0SC0 AMP0GN2 AMP0GN1 AMP0GN0 11111000
Bit5 Bit4
SYSCLK
------------------------------- - 1 –
× LK
2 C
SAR0
Rev. 1.2
R/W R/W R/W
Bit3 Bit2 Bit1
refers to the desired ADC0 SAR clock
SAR0
( >
AD0SC 00000b
R/W Reset Value
Bit0
)