Sequential Decoder/Demodulator Processor; Figure 5-3. Decoder Block Diagram - Comtech EF Data SDM-650B Installation And Operation Manual

SDM-650B Satellite Modem

5.2 Sequential Decoder/Demodulator Processor

The modem sequential decoder/demodulator processor is a 10.25" x 14" card that fits in
the middle-left slot of the modem chassis.
The card performs five separate functions:
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Refer to Figure 5-3 for a block diagram of the board. Refer to Section 5.2.2 for a detailed
description of the module.
MICRO-
COMPUTER
BUS
I CHANNEL
Q CHANNEL
Rev. 6
Contains the digital Costas processor which provides signals to the demodulator
board for carrier recovery and Automatic Gain Control (AGC)
Performs clock recovery of both the symbol clock and data clock
Provides the FEC function utilizing a sequential decoder
Provides differential decoding
Provides V.35 descrambling
MICROCOMPUTER
INTERFACE
SYNDROME
INPUT
GENERATOR
AMBIGUITY
RESOLVER
INPUT
BUFFER
COSTAS
PROCESSOR
VCXO
SW EEP
CLOCK
RECOVERY

Figure 5-3. Decoder Block Diagram

SYNDROME SHIFT
REGISTER A
PARITY
OUTPUT
GENERATOR
BUFFER
SYNDROM SHIFT
REGISTER B
ADDRESS LOCK
DETECT
GENERATOR
TIMING AND PROCESS
CONTROL CLOCK
Theory of Operation
V.35 RECEIVE
DESCRAMBLER
DATA
DIFFERENTIAL
DECODER
CHANNEL BER
DETECTOR
RECEIVE
CLOCK
RCVR
DDS
IF
AGC
CONTROL
5–7