Theory Of Operation; Demodulator Processor - Comtech EF Data SDM-650B Installation And Operation Manual

SDM-650B Satellite Modem

5.2.2 Theory of Operation

5.2.2.1 Demodulator Processor

The demodulator processor, in conjunction with the demodulator, reconstructs the digital
data stream that was transmitted but corrupted by transmission channel impairments.
The demodulator processor accepts 11-bit quantized signals from the demodulator for
both the I and Q channels.
Two of the levels are mainly used for clock recovery. The other nine channels are used
by the Costas calculator, and in generation of the 2-bit soft decision symbols required by
the sequential decoder.
The Costas calculator generates a phase error term from the I and Q channel quantized
data. This error term is scaled by input from the M&C, then is output to the analog
portion of the loop.
The sweep voltage, which is also controlled by the M&C, is summed with the integrated
error term, and is output from the board to drive the VCXO on the demodulator.
The clock loop is contained on this card. The clock loop consists of a phase-locked loop
with a VCXO for a reference. The phase-locked loop generates a clock, four times the
desired data rate. From this clock, dividers generate the data rate clock and the symbol
rate clock.
The symbol rate clock is compared with the quantized I and Q channel data to generate a
phase error term. The error term is scaled and integrated before it drives the VCXO on
the phase locked loop, thus closing the outer loop and driving the symbol rate clock to
synchronize to the incoming symbols.
The I and Q channel data is sampled and converted to 2-bit sign-magnitude form for use
by the sequential decoder.
Rev. 6
Theory of Operation
5–9