Sequential Decoder - Comtech EF Data SDM-650B Installation And Operation Manual

Theory of Operation

5.2.2.2 Sequential Decoder

The sequential decoder works in conjunction with the convolutional encoder at the
transmitting modem to correct bit errors in the received data stream from the
demodulator. The sequential decoder processes 2-bit quantized, I and Q channel data
symbols from the demodulator. This data is assumed to be a representation of the data
transmitted, corrupted by additive white Gaussian noise.
The decoder's task is to determine which bits have been corrupted by the transmission
channel, and correct as many as possible. The means to do this is provided by the parity
bits that the encoder adds to the input data stream prior to transmission.
The possible sequences of bits, including parity output by the encoder, is called a "code
tree." The decoder uses the parity bits and knowledge of the code tree to determine the
most likely correct sequence of data bits for a given received sequence.
The search proceeds from a node in the code tree by choosing the branch with the highest
metric value. The highest metric value is determined by the highest probability of a
match between the received data and a possible code sequence. The branch metrics are
added to form the cumulative metric.
As long as the cumulative metric increases at each node, the decoder assumes it is on the
correct path and continues forward.
If the decoder makes a wrong decision, the cumulative metric will decrease rapidly as the
error propagates through the taps of the parity generator. In this case, the decoder tries to
back up through the data to the last node where the metric was increasing, then take the
other branch.
In a severely erred environment, the decoder will continue to search backward for a path
with an increasing metric until it either finds one, runs out of buffered data, or runs out of
time, and must deliver the next bit to the output.
The decoder processes data at a fixed rate, which is much higher than the symbol rate of
the input data. This allows the decoder to evaluate numerous paths in its search for the
most likely path during each symbol time.
Data enters the input RAM of the decoder from the demodulator processor in 2-bit soft
decision form for both I and Q channels, as shown in the block diagram (Figure 5-7).
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SDM-650B Satellite Modem
Rev. 6