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SDM-650B Satellite Modem
The input RAM buffers the data to provide history for the backwards searches. Data from
the RAM passes through the ambiguity corrector, which compensates for the potential
90° phase ambiguity of the demodulator.
The syndrome input generator converts the 2-bit soft decision data into a single bit per
channel, and simultaneously corrects some isolated bit errors. The data is then shifted
through the syndrome shift registers, which allows the parity generator to detect bit
errors.
The resulting error signal provides the feedback to the timing and control circuitry to
allow it to direct the data along the path of the highest cumulative metric. The corrected
data is buffered through the output RAM and retiming circuit, which provides a data
stream at the constant rate of the data clock to the differential decoder and descrambler.
The data and the clock are then output from the card.
The sequential decoder provides the following built-in-test functions:
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The sequential decoder also provides a lock detect signal to the M&C when the error rate
has dropped below a threshold level. The M&C monitors these signals and takes
appropriate action.
The raw BER count is made by comparing the input and output decoder data. The output
data contains fewer errors than the input data.
Differences in the two data can be counted to yield the raw BER. The raw BER is sent to
the M&C for further processing.
Rev. 6
Activity detect on I and Q sign inputs
Activity detect of descrambler data
Raw BER detection
Theory of Operation
5–11
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