Figure 3-5. V.35 Interface Block Diagram - Comtech EF Data SDM-650B Installation And Operation Manual

SDM-650B Satellite Modem
SCT
TX CLOCK
M
TX DATA
O
D
RX CLOCK
E
M
RX DATA
COMMON EQUIPMENT
MODULATOR
DEMODULATOR
DATA BUS TO M & C
In either case, the phase relationship between the clock and data is not important as long
as the relationship meets the jitter specification. This is because a clock phase correction
circuit is provided, which shifts the clock away from the data transition times.
The clock selection is jumper-selectable at JP1 on the front edge of the board.
•
•
•
Rev. 5
LOOP TIMING
TO BUFFER
TO LOGIC CONTROL
OPTIONS
AUTO
CLOCK
SELECT
INVERT
NORM
TO BUFFER
OPTIONS
FAULT
RELAYS
CONTROL

Figure 3-5. V.35 Interface Block Diagram

When there is no jitter on the clock source, the Auto setting is used.
The Normal setting is used when standard specifications on clock and data
relationships exist.
The Invert mode is used when the incoming clock is inverted from the standard
clock and data relationship.
TO CONTROL LOGIC
LOOPBACK
TO CONTROL LOGIC
EXTERNAL BUFFER CLOCK
RTS TO CTS JUMPER
LOGIC
INT/EXT CLOCK
ST
TT
RT
T
SD
E
RD
R
R
E
S
T
MC
R
I
CS
A
RS
L
SPARE (RS-232 ONLY)
TTL MODULATOR FAULT
TTL DEMODULATOR FAULT
Configuration
3–15