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Trojan Interface
G.3 Specification
G.3.1 MIL-STD-188-114 Parameters
Circuit Supported
Amplitude (RD, RT, ST, DM, RR)
DC Offset (RD, RT, ST, DM, RR)
Impedance (RD, RT, ST, DM, RR)
Impedance (SD, TT, MC)
Polarity
Phasing (TT, RT)
Symmetry (ST, TT, RT)
Frequency Stability (ST)
Modulator Fault
Demodulator Fault
G.3.2 Clock Synthesizer/Dejitter Circuit
Reference Clk Sources
Reference Clk Input
Synthesized TX Clock
Synthesized RX Clock
Jitter Gain
G.3.3 Doppler Buffer Parameters
Buffer Size (bits)
Clock Source
Data Rate
Indicators
Controls
Misc.
G–6
SD, ST, TT, RD, RT, DM, RR, MC, MOD FAULT,
DEMOD FAULT.
4, ± 2V differential into 100Ω.
± 0.4V.
Less than 100Ω, differential.
100, ± 20Ω, differential.
True when B positive with respect to A.
False when A positive with respect to B.
False-to-true transition nominally in center of data bit.
50%, ± 5%.
± 100 ppm.
Open collector output, 15V max, 20 mA max current
sink. Fault is open circuit.
Open collector output, 15V max, 20 mA max current
sink. Fault is open circuit.
Transmit Clk
Receive Data Clk
External Reference Clk (MC)
Modem Internal Clk (SCT)
32 kHz to 10 MHz, in 8 kHz steps
56 to 2048 kHz, in 8 kHz steps
56 to 2048 kHz, in 8 kHz steps
Synth Clk Freq/Ref Clk Freq, modified by a 1-pole
(20 dB/decade) low-pass response corner at 0.4 Hz
512, 1024, 2048, 4096, 8192, 16384, 32768
Synthesized RX Clock
56 to 2048 kbit/s
Buffer Overflow (stored fault)
Buffer Underflow (stored fault)
Reset Buffer to Center
Buffer Depth
Buffer automatically recenters on Over/Underflow,
power-on, or start of service
SDM-650B Satellite Modem
Rev. 5
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