Video Output Registers; Video Output Registers Overview - NEC µPD72257 Preliminary User's Manual

Video Output

7.7 Video Output Registers

7.7.1 Video Output registers overview

Table 7-6
<VOn_Base> address
The Video Output is controlled and operated by means of the following registers:
Video Output registers overview
Register function
Horizontal axis panel control register VOnLCDTIMING0
Vertical axis panel control register
Clock and signal polarity control
register
Framebuffer base address register
Control register
Interrupt mask set/clear register
Raw interrupt status register
Masked interrupt status register
Interrupt clear register
Current address register
Colour palette registers
The <VOn_Base> addresses of the registers are defined in the first section of this
chapter under the key word "Register base addresses".
Preliminary User's Manual S19203EE1V3UM00
Name Address
<VOn_Base> + 000
<VOn_Base> + 004
VOnLCDTIMING1
<VOn_Base> + 008
VOnLCDTIMING2
<VOn_Base> + 010
VOnLCDUPBASE
<VOn_Base> + 018
VOnLCDCONTROL
<VOn_Base> + 01C
VOnLCDIMSC
<VOn_Base> + 020
VOnLCDRIS
<VOn_Base> + 024
VOnLCDMIS
<VOn_Base> + 028
VOnLCDICR
<VOn_Base> + 02C
VOnLCDUPCURR
<VOn_Base> + 200
VOnLCDPALETTE
<VOn_Base> + 3FC
Chapter 7
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