NEC µPD72257 Preliminary User's Manual page 141

Host CPU Interface
HOSTINTENAB
HOSTINTSTAT
HOSTSTATUS
HINT output
Figure 5-13
The HOSTINTENAB register applies an enable/mask bit HOSTINTENAB.INTENn
to each interrupt signal. An interrupt event signal INTINn is only activated if its
associated enable bit HOSTINTENAB.INTENn is 1.
The HOSTINTSTAT.INTSTAT[31:0] bits reflect the status of all active and enabled
- i.e. unmasked - interrupts. Hence in contrast to the HOSTINTFLAG register,
which shows all active interrupts, HOSTINTSTAT shows only active and
unmasked interrupts.
In addition to the separate interrupt flags for each of INT[31:0] in the
HOSTINTFLAG register the HOSTSTATUS register contains two status bits, that
reflect the status of each interrupt group:
• HOSTSTATUS.INTA = 1: at least one of the group A interrupts is
pending
• HOSTSTATUS.INTB = 1: at least one of the group B interrupts is
pending
The Host-I/F interrupt request signal HINT stays active as long as any
HOSTINTSTAT.INTSTAT[31:0] is 1.
Following diagram gives an example of an interrupt request and reset process.
INT0
signal
HOSTINTFLAG.
INTIN0
INT16
signal
HOSTINTFLAG.
INTIN16
HOSTINTENAB.
INTEN0
HOSTINTENAB.
INTEN16
HOSTINTSTAT.
INTSTAT0
HOSTINTSTAT.
INTSTAT16
HINT
Write
HOSTINTFLAG
.INTSTAT0 = 1
Interrupt processing example
Preliminary User's Manual S19203EE1V3UM00
Chapter 5
141