Lbus Interface; Lbus-I/F Signals - NEC µPD72257 Preliminary User's Manual

Host CPU Interface
Figure 5-1

5.2 LBus Interface

5.2.1 LBus-I/F signals

HLBD[7:0] HLBWR HLBDRQ
HLBCS HLBRD
LBus-I/F
iDATA[31:0]
Address decoder
HIFSEL APB
Host-I/F block diagram
The LBus-I/F achieves minimum signal count to the Host CPU by using only an
8-bit data bus HLBD[7:0] for transferring addresses as well as data. Therefore a
dedicated protocol in form of five commands is used.
Beside direct (28-bit long) addressing a (24-bit) short offset addressing mode is
provided in order to unload the LBus. Additionally a burst transfer mode with
automatic address incrementing functions minimizes the overhead of address
transfers and offers maximum data transfer bandwidth.
The data width can be specified to be byte, half-word and word.
If enabled, the signal HLBDRQ is generated if the LBus-I/F is ready to accept the
next data transfer. The Host CPU can employ this signal as an interrupt or DMA
trigger, thus avoiding standby times.
The Host CPU communicates with the LBus-I/F via following signals:
• 8-bit data I/O bus HLBD[7:0]
• write strobe HLBWR
• read strobe HLBRD
• chip select HLBCS
• data request HLBDRQ
Preliminary User's Manual S19203EE1V3UM00
HADD[15:0] HADWR HADWAIT
HADCS HADRD
ADBus-I/F
iADDR[27:0]
Host-I/F
registers
AHB
Chapter 5
HADA[20:0]
HINT
HADBEN[1:0]
Interrupt
controller
Host-I/F
interrutps
HCLK Group A Group B
interrutps interrutps
123