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Video Output
7.7.2.9
Access
Address
Initial Value
31
30
29
28
0
0
0
0
W
W
W
W
15
14
13
12
0
0
0
0
W
W
W
W
Bit
Bit name
4
MBERRORIC
3
VCOMPIC
2
LNBUIC
1
FUFIC
VOnLCDICR - Interrupt clear register
This register allows to clear a pending system interrupt.
The pending system interrupts are monitored in the VOnLCDMIS register. Writing
"1" to the respective bit in this register clears its system interrupt and
consequently clears also its corresponding bit in VOnLCDMIS.
This register can be written in 32-bit units.
<VOn_Base> + 028
H
none
27
26
25
24
0
0
0
0
W
W
W
W
11
10
9
8
0
0
0
0
W
W
W
W
Reading this register returns an undefined value.
Function
Clear AHB master error sytem interrupt
Clear is performed by writing 1.
Clear Vertical compare sytem interrupt
Clear is performed by writing 1.
Clear LCD next address base update sytem interrupt
Clear is performed by writing 1.
Clear FIFO underflow sytem interrupt
Clear is performed by writing 1.
Preliminary User's Manual S19203EE1V3UM00
23
22
21
20
0
0
0
0
W
W
W
W
7
6
5
4
MBER
0
0
0
ROR
IC
W
W
W
W
Chapter 7
19
18
17
16
0
0
0
0
W
W
W
W
3
2
1
0
VCO
LNBU
FUF
MP
0
IC
IC
IC
W
W
W
W
213
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