Table of Contents
Advertisement
Host CPU Interface
(a)
(b)
•
first half-word accesses on word aligned address, i.e. HADBEN
[1:0] = 00
, HADA[1:0] = 00
B
•
second half-word on next halfword address, i.e. HADBEN[1:0] =
00
, HADA[1:0] = 10
B
Combined write access
If a ADBus write is performed with HADBEN[1:0] = 00
assumed to be the first half-word of a word write. Thus a half-word and its address
is buffered.
If the next ADBus-I/F write is performed with HADBEN[1:0] = 00
= 10
, both half-words are combined to a word, which is forwarded to its
B
destination.
In case the first half-word write (with HADBEN[1:0] = 00
immediately followed by a
•
byte write access (HADBEN[1:0] = 10
•
half-word write access to an address unequal the next halfword
address HADA[1:0] = 10
•
read access
the word combining process is disrupted and the write accesses are treated as
consecutive separate writes. Both half-words are separately forwarded to their
destinations.
Combined read access
If a ADBus read is performed with HADBEN[1:0] = 00
assumed to be the first half-word of a word read. Thus a word is acquired from
the addressed source and the lower half-word is passed on to the ADBus-I/F.
If the next ADBus access is a half-word read with HADBEN[1:0] = 00
[1:0] = 10
, the upper half-word is made available on to the ADBus-I/F
B
immediately.
In case the first half-word read is immediately followed by a
•
byte read access (HADBEN[1:0] = 10
•
half-word read access to an address unequal the next half-word
address HADA[1:0] = 10
•
write access
Preliminary User's Manual S19203EE1V3UM00
B
B
, 01
B
B
B
, 01
B
B
B
Chapter 5
and HADA[1:0] = 00
B
and HADA[1:0]
B
and HADA[1:0] = 00
B
or 11
)
B
and HADA[1:0] = 00
B
and HADA
B
or 11
)
B
, it is
B
) is
B
, it is
B
135
Advertisement
Table of Contents
