Block Diagrams - NEC µPD72257 Preliminary User's Manual

Chapter 1

1.1 Block diagrams

HLBD[7:0]
HLBWR
HLBRD
HLBCS
HLBDRQ
Host-I/F
HINT
HADD[15:0]
HADBEN[1:0]
HADA[20:0]
HADWR
HADRD
HADCS
HADWAIT
VI0R[5:0]
VI0G[5:0]
VI0B[5:0]
ITU0[7:0]
Video
VI0CLK
Input
VI0SYNC1
VI0SYNC2
VO0R[5:0]
VO0G[5:0]
Video
VO0B[5:0]
Output
VO0HSYNC
VO0VSYNC
VO0CLK
VO0EN
VO1R[5:0]
VO1G[5:0]
Video
VO1B[5:0]
Output
VO1HSYNC
VO1VSYNC
VO1CLK
Figure 1-1
12
The block diagrams below show the functional modules of Ravin-M and Ravin-L,
the bus systems and the external signals.
APB
APB master
HCLK
SYSRESET
AHB master
APB slave
HCLK
AHB master
AHB slave
SYSRESET
VO0CLK
0
AHB master
AHB slave
VO1CLK
1
SYSRESET
AHB master
Ravin-M block diagram
Preliminary User's Manual S19203EE1V3UM00
Ravin-M
AHB
AHB master
Drawing
HCLK
Engine
SYSRESET
APB slave Slave
HCLK
AHB slave
SYSRESET
HCLK
VO0CLK
System
SYSRESET
Controller
APB slave
VO1CLK
Introduction
MD[31:0]
MA[24:0]
MCS0
MCS1
MDBA[1:0]
MDDQM[3:0]
MDRAS
MDCAS
MDWE
MDCKE
MDCLK
MDFBCLK
MDA10PC
MSOE
MSWR
MSBEN[3:0]
RESET
XT1
XT2