Register List
Address
0000 1D40H
Limiter 1 y-axis increment
0000 1D44H
Limiter 2 y-axis increment
0000 1D48H
Limiter 3 y-axis increment
0000 1D4CH
Limiter 4 y-axis increment
0000 1D50H
Limiter 5 y-axis increment
0000 1D54H
Limiter 6 y-axis increment
0000 1D58H
Limiter 1 band width parameter
0000 1D5CH
Limiter 2 band width parameter
0000 1D64H
Base color
0000 1D68H
Secondary color
0000 1D74H
Pattern register
0000 1D78H
Bounding box dimension
0000 1D7CH
Framebuffer pitch and spanstore delay
0000 1D80H
Framebuffer base address
0000 1D90H
U Limiter start value
0000 1D94H
U Limiter x-axis increment
0000 1D98H
U Limiter y-axis increment
0000 1D9CH
V Limiter start value integer part
0000 1DA0H
V Limiter start value fractional part
0000 1DA4H
V Limiter x-axis increment integer part
0000 1DA8H
V Limiter y-axis increment integer part
0000 1DACH
V Limiter increment fractional parts
0000 1DB4H
Texels per texture line
0000 1DB8H
Texture size or texture address mask
0000 1DBCH
Texture base address
0000 1DC0H
Interrupt control
0000 1DC4H
Cache control
0000 1DC8H
Displaylist start address
0000 1DCCH
Performance counter 1
0000 1DD0H
Performance counter 2
0000 1DD4H
Performance counters control register
0000 1DD8H
Colour lookup table for the indexed texture format
0000 1E00H
First field framebuffer memory start address
0000 1E04H
Second field framebuffer memory start address
0000 1E08H
First pixel
0000 1E0CH
First line
0000 1E10H
Scaled pixels/line
0000 1E14H
Scaled lines/field
0000 1E18H
Video Input control
0000 1E1CH
Scaling factors
Register name
Preliminary User's Manual S19203EE1V3UM00
Access width in
Shortcut
DRWL1YADD
–
DRWL2YADD
–
DRWL3YADD
–
DRWL4YADD
–
DRWL5YADD
–
DRWL6YADD
–
DRWL1BAND
–
DRWL2BAND
–
DRWCOLOR1
–
DRWCOLOR2
–
DRWPATTERN
–
DRWSIZE
–
DRWPITCH
–
DRWORIGIN
–
DRWLUSTART
–
DRWLUXADD
–
DRWLUYADD
–
DRWLVSTARTI
–
DRWLVSTARTF
–
DRWLVXADDI
–
DRWLVYADDI
–
DRWLVYXADDF
–
DRWTEXPITCH
–
DRWTEXMASK
–
DRWTEXORIGIN
–
DRWIRQCTL
–
DRWCACHECTL
–
DRWDLISTSTART
–
DRWPERFCOUNT1
–
DRWPERFCOUNT2
–
DRWPERFTRIGGER
–
DRWTEXCLUT
–
VI0STARTADDR1
–
VI0STARTADDR2
–
VI0STARTX
–
VI0STARTY
–
VI0SCALEDWIDTH
–
VI0SCALEDHEIGHT
–
VI0CONTROL
–
VI0SCALING
–
Chapter 10
bit
8
16
32
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
R/W
–
R/W
–
W
–
W
–
R/W
–
R/W
–
R/W
–
R/W
–
R/W
–
R/W
–
R/W
–
R/W
333