NEC µPD72257 Preliminary User's Manual page 131

Host CPU Interface
5.2.3.6
(1)
(2)
(3)
Reset
Illegal interruption of the command-data flow
The Host CPU has strictly to follow the above defined command-data flow
schemes.
In case the Host CPU applies erroneous read-write sequences, the LBus-I/F
reacts as follows:
The Host CPU issues a read access while the LBus-I/F expects a write
The LBus-I/F returns the contents of the HOSTSTATUS register to the Host CPU
and resets its internal command-data flow mechanism. Afterwards the Host CPU
can restart to send new commands.
The Host CPU writes after the first command byte none or too less command
and/or data bytes
The LBus-I/F keeps on waiting for further bytes from the Host CPU. The Host CPU
shall write one byte, followed by a byte read in order to reset the LBus-I/F's
command-data flow mechanism. Afterwards the Host CPU can restart to send
new commands.
The Host CPU initiates data read transfers but doesn't perform any further
read
The LBus-I/F keeps on waiting for further read from the Host CPU. The Host CPU
shall write one byte, followed by a read in order to reset the LBus-I/F's command-
data flow mechanism. Afterwards the Host CPU can restart to send new
commands.
The Host CPU can utilize this behaviour similar to a "reset" command to cancel
any command-data flow deadlock between itself and the LBus-I/F by the
following sequence:
• write one byte
• read one byte
Thereby the LBus-I/F will return the HOSTSTATUS register content to the Host
CPU and reset its command-data flow mechanism. Afterwards new data transfers
can be initiated by the Host CPU.
Preliminary User's Manual S19203EE1V3UM00
Chapter 5
131