NEC µPD72257 Preliminary User's Manual page 195

Graphics controllers
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Video Output
VOnHSYNC
HFP
VOnHSYNC
IHS = 0
VOnHSYNC
IHS = 1
VOnEN
IOE = 0
VOnEN
IOE = 1
Figure 7-3
VOnVSYNC
The diagram below illustrates the line synchronization timing settings.
The video data enable signal VOnEN is derived from the other timing values:
VOnEN width in pixels = pixels/line - horizontal (front porch + back porch + sync
pulse width)
The active level of the VOnHSYNC and VOnEN signals can be defined as follows:
active level of VOnHSYNC
-
VOnLCDTIMING2.IHS = 0: VOnHSYNC is active high
-
VOnLCDTIMING2.IHS = 1: VOnHSYNC is active low
active level of VOnEN
-
VOnLCDTIMING2.IOE = 0: VOnEN is active high
-
VOnLCDTIMING2.IOE = 1: VOnEN is active low
PPL
HSW
HBP
VOnHSYNC timing setting
The diagram below illustrates the line synchronization timing settings.
The active level of the VOnVSYNC signal can be defined as follows:
active level of VOnVSYNC
-
VOnLCDTIMING2.IVS = 0: VOnVSYNC is active high
-
VOnLCDTIMING2.IVS = 1: VOnVSYNC is active low
The point in time to generate the vertical compare interrupt VOnVCPINT, that
indicates the start of a new frame, can be chosen as follows:
VOnVCPINT interrupt timing
-
VOnLCDCONTROL.LCDVCOMP[1:0] = 00
HSYNC pulse
-
VOnLCDCONTROL.LCDVCOMP[1:0] = 01
porch
-
VOnLCDCONTROL.LCDVCOMP[1:0] = 10
active video data
-
VOnLCDCONTROL.LCDVCOMP[1:0] = 11
porch
Preliminary User's Manual S19203EE1V3UM00
Video data valid
Chapter 7
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