NEC µPD72257 Preliminary User's Manual page 291

External Memory Interface Controller
Bus Signal
MSBEN0
MSBEN1
MSBEN2
MSBEN3
Ravin-L pin functions
SDRAM clock enable
Default configuration
1, 9 2, 7e
– √
– √
– –
– –
The Ravin-L external memory I/F signals are:
• Shared signals:
- MA[24:0]
- MD[15:0]
- MCS0
- MCS1
• SDRAM signals:
- MDBA[1:0]
- MDDQM0
- MDDQM1
- MDRAS
- MDCAS
- MDWE
- MDCKE
- MDCLK
- MDFBCLK
- MDA10PC
• Static memory signals:
- MSOE
- MSWR
- MSBEN0
- MSBEN1
When using SDRAM the external memory clock MDCLK needs to be enabled by
setting SYSCLKCTRL.SDREN = 1 in the System Controller.
The default value of SYSCLKCTRL.SDREN is determined by the level of the
MODE7 pin at RESET release. Thus the external memory interface may be
enabled or disabled at system start-up.
Upon system start-up the external memory interface is configured as follows:
• MCS0: 16 MB SDRAM, 32-bit data bus width, base and alias address
0000 0000
H
- 8 bit column address, 11 bit row address, 4 banks
- 7 clocks after self-refresh exit, 7 clocks active-to-active
command, 7 clocks after auto-refresh
- 1 clock from last data to next precharge, 3 clocks precharge
period, 2 clocks between active and read/write command, 5
clocks min. delay between active and precharge
- 3 clocks CAS latency
- 8 auto-refresh during initialization, 8 clocks bus stable after
power-up
- 2 banks open, 1 row refresh before and after self-refresh, row
kept open after read/write operation
- 1040 clocks refresh period
Preliminary User's Manual S19203EE1V3UM00
Ravin-M option
3 6 7a, 7b
√ – √
√ – √
√ – –
√ – –
Chapter 9
7c 7d
√ √
√ √
– –
– –
291