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External Memory Interface Controller
9.4 Address Decoder
Figure 9-10
9.4.1 Chip select configuration
The Memory Controller is linked to the other internal modules via its AHB slave
interface. The internal address IMEMADD[31:0] of the external memory to be
accessed are transfered via the 32-bit AHB address bus. IMEMADD[31:0] always
represents a byte address.
IMEMADD[31:0] is supplied to the chip select decoder, that generates the external
chip select signals MCSn, in accordance with the settings of the MEMSCSLRn,
MEMCSALIASn and MEMSMSKRn registers.
IMEMADD[31:0] is also passed on to an address adjustment unit, that eliminates
unnecessary least significant address bits with regard to the data bus width of the
externally connected memory devices, as defined in MEMSCONR respectively
MEMSMCTRL registers.
IMEMADDR[31:0]
Address decoder
Each chip select area MCSn can be configured to operate with different types of
external memory devices.
The configuration for each chip select area is achieved by means of a register set,
dedicated to each MCSn.
Following separate registers, dedicated to each MCSn, are provided:
•
chip select mask registers MEMSMSKRn
•
chip select base address registers MEMSCSLRn
•
chip select alias registers MEMCSALIASn
The type of memory and its size for MCSn is chosen by the chip select mask
registers MEMSMSKRn:
•
memory type:
-
MEMSMSKRn.MEMTYPE[2:0] = 000
-
MEMSMSKRn.MEMTYPE[2:0] = 001
-
MEMSMSKRn.MEMTYPE[2:0] = 010
Preliminary User's Manual S19203EE1V3UM00
MEMSMSKRn.MEMSIZE
MEMSCSLRn
MEMCSALIASn
Chip select
decoder
Address
adjustment
MEMSCONR.DDATAW
MEMSMCTRL.SDATAW
: SDRAM for MCSn
B
: static RAM for MCSn
B
: flash for MCSn
B
Chapter 9
MCSn
MA[24:0]
307
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