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External Memory Interface Controller
9.6.2.2
Access
Address
Initial Value
31
30
29
28
TEXSR[4:0]
R/W
15
14
13
12
TRCAR[1:0]
TWR[1:0]
R/W
R/W
Caution
Bit
Bit name
31 to 27
TEXSR[4:0]
21 to 18
TXSR[3:0]
25 to 22
TRC[3:0]
17 to 14
TRCAR[3:0]
MEMSTMG0R - SDRAM timing register 0
This register defines various timing parameters of the SDRAM interface.
All values are given in system clock periods 1/f
This register can be read/written in 32-bit units.
<MemC_Base> + 04
H
0199 8452
. This register is initialized by any reset.
H
27
26
25
24
0
TRC[3:0]
R/W
11
10
9
8
TRP[2:0]
R/W
The default value "0" of bit 26 must not be changed.
Function
TEXSR[4:0] and TXSR[3:0] define the time between exit of SDRAM self-refresh mode by
setting MEMCTRL.SREF = 0 and the start of the auto-refresh mode respectively data
transfer command.
The number of system clocks is calculated by TEXSR[4:0] << 4 + TXSR[3:0]
000
1 clock
H
001
2 clocks
H
...
...
006
7 clocks (default)
H
...
...
1FF
512 clocks
H
TRC[3:0] defines the active-to-active command period.
0
1 clock
H
1
2 clocks
H
...
...
6
7 clocks (default)
H
...
...
F
16 clocks
H
TRCAR[3:0] defines the minimum time to wait after auto-refresh before a next auto-
refresh or any other command is performed.
0
1 clock
H
1
2 clocks
H
...
...
6
7 clocks (default)
H
Preliminary User's Manual S19203EE1V3UM00
HCLK
23
22
21
R/W
7
6
5
TRCD[2:0]
TRASMIN[3:0]
R/W
Chapter 9
.
20
19
18
17
TXSR[3:0]
TRCAR[3:2]
R/W
R/W
4
3
2
1
CASLAT[1:0]
R/W
R/W
16
0
317
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