NEC µPD72257 Preliminary User's Manual page 180

Chapter 6
6.10.2.8
Interlaced scan
Progressive scan
Access
Address
Initial Value
31 30 29 28
0 0 0 0
R R R R
15 14 13 12
0 0 0 0
R R R R
Bit Bit name
25 to 16 STARTY2[9:0]
9 to 0 STARTY1[9:0]
180
VInSTARTY - First line register
This register defines the first valid scanline of the first and second field to process.
An internal line counter counts all incoming lines and is reset with every VSYNC.
If this line counter equals STARTY[9:0], all following lines of the same field are
passed on for further processing.
In the case of interlaced video it is possible to use independent values for even
and odd field.
In case of progressive video only STARTY2[9:0] defines the first line to capture,
whereas STARTY1[9:0] is disregarded.
This register can be read/written in 32-bit units.
<VIn_Base> + 0C
H
0000 0000 . This register is initialized by any reset.
H
27 26 25 24
0 0
R R
11 10 9 8
0 0
R R
Writing to the read-only bits is ignored, reading returns undefined values.
Function
First valid line of the second field to be processed
First valid line of the first field to be processed
Preliminary User's Manual S19203EE1V3UM00
Video Input (Ravin-M only)
23 22 21 20
STARTY2[9:0]
R/W
7 6 5 4
STARTY1[9:0]
R/W
19 18 17 16
3 2 1 0