NEC µPD72257 Preliminary User's Manual page 148

Chapter 5
5.7.2.5
Interrupt n
Access
Address
Initial Value
31 30 29 28
15 14 13 12
Bit Bit name
31 to 17 INTIN[31:17]
16 to 3 INTIN[16:3]
2 INTIN2
1 INTIN1
0 INTIN0
148
HOSTINTFLAG - Interrupt input register
The interrupt enable register enables or masks the interrupt n.
The available interrupt of this device are defined in the first section of this chapter
under the key word "Interrupts".
The interrupt status bits of the two interrupt groups are treated differenctly:
• INT[31:17] reflect the status of the group B interrupts, thus these bits
can only be read.
• INT[15:0] reflect the status of the group A interrupts. These bits can
be set back to "0" by writing "1" to the concerned bit position.
This register can be read/written in 32-bit units.
0000 0018
H
0000 0000 . This register is initialized by any reset.
H
27 26 25 24
INTIN[31:17]
11 10 9 8
INTIN[15:3]
R/W
Writing to the read-only bits is ignored.
Function
Status of interrupt n
0 interrupt n not asserted
1 interrupt n asserted
Writing "1" clears the bit to "0", writing "0" has no effect.
Status of interrupt n
0 interrupt n not asserted
1 interrupt n asserted
Status of AHB_ERR interrupt
0 AHB_ERR interrupt not asserted
1 AHB_ERR interrupt asserted
Status of AHB_OVERRUN interrupt
0 AHB_OVERRUN not asserted
1 AHB_OVERRUN interrupt asserted
Status of AHB_UNDERRUN interrupt
0 AHB_UNDERRUN interrupt not asserted
1 AHB_UNDERRUN interrupt asserted
Preliminary User's Manual S19203EE1V3UM00
23 22 21 20
R
7 6 5 4
Host CPU Interface
19 18 17 16
3 2 1 0
INT INT INT
IN2 IN1 IN0
R/W R/W R/W