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Chapter 5
Figure 5-2
Note
5.2.2 LBus-I/F addressing modes
(1)
(2)
(3)
124
The principle timing of the LBus-I/F is shown in the following diagram.
LBCS
LBWR
LBRD
LBD[7:0]
LBD[7:0]
LBus-I/F principle timing
For information concerning the exact timing requirements refer to the Preliminary
Data Sheet.
Three different addressing modes are provided:
Short addressing mode
A 24-bit address is composed of a 12-bit offset and a 12-bit address.
The upper 12 bit of the address are set up by the dedicated command
eeShortOffs, prior to the short address data transfer command eeShort. These
upper 12 bit are retained until overwrite with the next eeShortOffs.
The eeShort command defines the lower 12 bit of the entire address and initiates
the data transfer. Thus the short addressing mode allows fast access to a 4 KB
data segment by the 2-byte eeShort command.
Since short addressing generates a 24-bit address, the address range is limited
to the first 16 MB of the entire 28-bit address range.
The data length can be defined within the eeShort command as byte, half-word
or word.
Long addressing mode
In this mode the entire 28-bit address is described in the 4-byte eeLong
command, which initiates also the data transfer. Long addressing mode allows
random access to the entire 28-bit address range
The data length can be defined within the eeLong command as byte, half-word
or word.
Burst addressing mode
Preliminary User's Manual S19203EE1V3UM00
Host CPU Interface
Read data
Write data
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