Table of Contents
Advertisement
Chapter 7
7.7.2.4
Access
Address
Initial Value
31
30
29
28
0
0
0
0
R
R
R
R
15
14
13
12
LCDVCOMP
0
0
[1:0]
R
R
R/W
a
The default value "0" of bit 5 must be changed to "1" after reset.
Caution
Bit
Bit name
16
WATERMARK
LCDVCOMP
13 to 12
[1:0]
11
LCDPWR
206
VOnLCDCONTROL - Control register
This register controls the Video Output operating mode and the pixel parameters.
This register can be read/written in 32-bit units.
<VOn_Base> + 018
H
0000 0000
. This register is initialized by any reset.
H
27
26
25
24
0
0
0
0
R
R
R
R
11
10
9
8
LCD
0
0
BGR
PWR
R/W
R/W
R/W
R/W
Bits marked as read-only must be written with "0", reading returns undefined
values.
1.
Bit 5 of VOnLCDCONTROL must be set to "1" after reset and must
not be altered afterwards.
2.
The default value "0" of bit 10 to 9, 7 to 6 and 4 must not be changed.
Function
DMA FIFO watermark level
WATERMARK defines the number of empty locations in the DMA FIFO to initiate new
data read from the framebuffer.
0
≥ 4 empty locations
1
≥ 8 empty locations
Vertical compare interrupt control
LCDVCOMP[1:0] defines the time to generate the VOnVCPINT.
00
start of vertical synchronization pulse VSYNC
B
01
start of back porch
B
10
start of active video data output
B
11
start of front porch
B
Display data signals power enable
LCDPRW = 1 enables the display data signals VOnR[5:0], VOnG[5:0], VOnB[5:0].
0
display data signals disabled (output low level)
1
display data signals enabled (active)
Activating of the display data signals requires to enable the Video Output control signals
by LCDEN = 1 prior setting LCDPWR = 1.
Preliminary User's Manual S19203EE1V3UM00
23
22
21
20
0
0
0
0
R
R
R
R
7
6
5
4
a
0
0
0
1
R/W
R/W
R/W
R/W
Video Output
19
18
17
16
WATE
0
0
0
R
MARK
R
R
R
R/W
3
2
1
0
LCD
LCDBPP[2:0]
EN
R/W
R/W
Advertisement
Table of Contents
