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Host CPU Interface
5.2.3.2
Byte
Bit
15
14
Content
Parameters
L[1:0] = 00
eeShort byte1
B
data byte
L[1:0] = 01
eeShort byte1
B
data byte1
L[1:0] = 10
eeShort byte1
B
data byte1
Figure 5-4
eeShort command
This command initiates a data access in short (24-bit) addressing mode. The
address ADD[27:0] that is accessed with eeShort is calculated as follows:
ADD[27:0] = 0x0FF FFFF & ( (SHADDOFF[11:0] << 12) or LADD[11:0] )
2nd byte
13
12
11
10
LADD[11:4]
•
bit1 = RW: defines the direction of the data transfer:
-
RW = 0: write mode, LBDIN[7:0] from Host CPU (HLBWR active)
-
RW = 1: read mode, LBDIN[7:0] to Host CPU (HLBRD active)
•
bit[3:2] = L[1:0]: defines the data length, i.e. the number of data bytes
to transfer:
-
L[1:0] = 00
B
-
L[1:0] = 01
B
-
L[1:0] = 10
B
-
L[1:0] = 11
B
•
bit[15:4] = LADD[11:0]: lower 12 bit of the address
eeShort byte2
eeShort byte2
data byte2
eeShort byte2
data byte2
eeShort command flow
Preliminary User's Manual S19203EE1V3UM00
9
8
7
6
LADD[3:0]
: 1 data byte (8-bit data)
: 2 data bytes (16-bit data)
: 4 data bytes (32-bit data)
: setting prohibited
data byte3
data byte4
Chapter 5
1st byte
5
4
3
2
L[1:0]
RW
command
transfer
byte
data transfer
command
transfer
halfword
data transfer
command
transfer
word
data transfer
1
0
0
127
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