NEC µPD72257 Preliminary User's Manual page 320

Chapter 9
9.6.2.4
Access
Address
Initial Value
31 30 29 28
0 0 0 0
R R R R
15 14 13 12
OPENBK[3:0]
R/W
Caution
Bit Bit name
16 to 12 OPENBK[4:0]
11 SREFSTAT
9 SDRMODE
5 FSREFA
4 FSREFB
320
MEMSCTLR - SDRAM control register
This register controls various functions of the SDRAM controller.
This register can be read/written in 32-bit units.
<MemC_Base> + 0C
H
0000 1088 . This register is initialized by any reset.
H
27 26 25 24
0 0 0 0
R R R R
11 10 9 8
SDR
SREF
0 MOD 0
STAT
E
R R R/W R/W
Writing to the read-only bits is ignored, reading returns undefined values.
The default value "010
B
Function
OPENBK[4:0] defines the number of SDRAM internal banks to be open at any time
00
1 bank open
H
01
2 banks open (default)
H
10
...
H
1F
31 banks open
H
SREFSTAT reflects the status of entering the SDRAM self-refresh mode.
Depending on whether all rows or one row are refreshed - defined by
MEMSCTRL.FSREFB - before entering self-refresh mode, it may take some time before
SDRAM is put into self-refresh mode. SREFSTAT = 1 indicates the completion of this
process.
0 SDRAM not in self-refresh mode
1 SDRAM in self-refresh mode
By SDRMODE the Memory Controller can be forced to do update of SDRAM devices'
mode registers.
0 update completed
1 forces update of SDRAM mode registers
This bit is cleared automatically if the SDRAM mode register update is finished.
FSREFA controls the number of refreshes done after SDRAM is taken out of self-refresh
mode
0 refresh one row (default)
1 refresh all rows
FSREFB controls number of refreshes done before entering SDRAM self-refresh mode
0 refresh one row (default)
Preliminary User's Manual S19203EE1V3UM00
External Memory Interface Controller
23 22 21
0 0 0
R R R
7 6 5
FSRE
1 0
FA
R/W R/W R/W
" of bits 8 to 6 must not be changed.
20 19 18 17
0 0 0 0
R R/W R/W R/W
4 3 2 1
FSRE PRC PWD
SREF
FB HALG M
R/W R/W R/W R/W
16
OPE
NBK4
0
INIT
R/W