NEC µPD72257 Preliminary User's Manual page 204

Chapter 7
7.7.2.3
Access
Address
Initial Value
31 30 29 28
0 0 0 0
R/W R/W R/W R/W
15 14 13 12
0 IOE IPC IHS
R R/W R/W R/W
a
The default value "0" of bit 26 must be changed to "1" after reset.
Caution
Bit Bit name
26 bit 26
25 to 16 CPL[9:0]
14 IOE
13 IPC
12 IHS
11 IVS
204
VOnLCDTIMING2 - Clock and signal polarity control register
This register defines various properties of the control signals:
• polarity of synchronization and data enable signals
• valid edge VOnCLK pixel clock
• number of pixel clocks/line
This register can be read/written in 32-bit units.
<VOn_Base> + 008
H
0000 0000 . This register is initialized by any reset.
H
27 26 25 24
0 a
1
R/W R/W
11 10 9 8
IVS 0 0 0
R/W R/W R/W R/W
Bits marked as read-only must be written with "0", reading returns undefined
values.
1. Bit 26 of VOnLCDTIMING2 must be set to "1" after reset and must
not be altered afterwards.
2. The default value "0" of bit 31 to 27 and 10 to 0 must not be changed.
Function
The default value "0" of this bit must be changed to "1" after reset and must not be altered
afterwards.
Number of VOnCLK clocks per line
CPL[9:0] specifies the number of VOnCLK clocks to the LCD display on each line. This
equals the number of pixels/line, as specified by VoOnLCDTiming0.PPL[5:0].
Thus set CPL[9:0] = 16 • (VOnLCDTiming0.PPL[5:0] + 1)
Video data enable VOnEN active level
0 VOnEN is active high
1 VOnEN is active low
VOnCLK edge selection
0 display data out with rising edge of VOnCLK, i.e. data stable at falling edge
1 display data out with falling edge of VOnCLK, i.e. data stable at rising edge
Horizontal synchronization VOnHSYNC active level
0 VOnHSYNC is active high and inactive low
1 VOnHSYNC is active low and inactive high
Vertical synchronization VOnVSYNC active level
0 VOnVSYNC is active high and inactive low
1 VOnVSYNC is active low and inactive high
Preliminary User's Manual S19203EE1V3UM00
23 22 21 20
CPL
R/W
7 6 5 4
0 0 0 0
R/W R/W R/W R/W
Video Output
19 18 17 16
3 2 1 0
0 0 0 0
R/W R/W R/W R/W